Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts sensor

• US 8,966,193 B2
• Filed: 06/30/2011
• Issued: 02/24/2015
• Est. Priority Date: 06/16/2005
• Status: Active Grant

• Current Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Original Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Inventors: Booth, James Ronald, Willett, Bryan Scott
• Primary Examiner(s): Dudek, Jr., Edward
• Assistant Examiner(s): CHRZANOWSKI, MATTHEW R
• Application Number:
  US13/174,759
• Publication Number:
  US 20110264850A1
• Time in Patent Office: 1,335 Days
• Field of Search: None
• US Class Current: 711/156
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, a punch out bit field, or a cryptographic command. The commands may be transmitted using a broadcast scheme or a split transaction scheme. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level.

Claims

1. A method of updating a memory module, comprising:

receiving, at a memory module, a command indicative of usage of toner or ink in a consumable item for an imaging device for instructing the memory module to punch out at least one bit of at least one specified bit field within the memory module indicative of the usage of toner or ink; and

processing the command at the memory module.

2. The method of claim 1, wherein the processing of the command comprises changing the at least one bit from an erased state to a programmed state.

3. The method of claim 1, wherein the at least one bit comprises a plurality of bits and the at least one specified bit field comprises a plurality of separately specified bit fields such that each bit corresponds to a distinct specified bit field.

4. The method of claim 3, wherein the plurality of bits comprises at least eight bits.

5. The method of claim 1, further comprising receiving a second command, wherein the second command is operable to instruct the memory module to increment a non-volatile counter therein.

6. The method of claim 5, wherein the processing comprises incrementing the counter by an amount specified in the command.

7. The method of claim 5, wherein the processing comprises processing the command and the second command, including at least one of changing the at least one bit from an erased state to a programmed state and incrementing the counter.

8. The method of claim 7, wherein incrementing the counter comprises incrementing the counter by an amount specified in the command.

9. The method of claim 1, wherein the processing comprises:

upon encountering an error condition while processing the command, limiting voltages on a first interface signal line of the memory module to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state.

10. A memory module, comprising:

a plurality of memory bits, wherein the memory module receives at least one command indicative of usage of toner or ink in a consumable item for an imaging device and instructs the memory module to punch out at least one bit in at least one specified bit field within the memory module indicative of the usage of toner or ink, and processes the at least one command.

11. The memory module of claim 10, wherein the memory module processes the at least one command by changing the at least one bit in the at least one specified bit field from an erased state to a programmed state.

12. The memory module of claim 10, wherein the at least one bit comprises a plurality of bits and the at least one specified bit field comprises a plurality of separately specified bit fields, each bit corresponding to a distinct bit field.

13. The memory module of claim 10, wherein the memory module includes a non-volatile counter and the at least one command includes a second command for instructing the memory module to increment the non-volatile counter therein.

14. The memory module of claim 13, wherein the memory module processes the at least one command by changing the at least one bit in the at least one specified bit field from an erased state to a programmed state and incrementing the non-volatile counter.

15. The memory module of claim 14, wherein the memory module processes the at least one command by incrementing the non-volatile counter by an amount specified in the at least one command.

16. The memory module of claim 10, wherein the memory module includes a first interface signal line for communicating with a processing device, the memory module processes the at least one command by:

upon encountering an error condition while processing the at least one command, limiting voltages on the first interface signal line to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time to indicate an occurrence of the error condition.

17. A memory module, comprising:

a plurality of memory cells; and

a plurality of signal lines for communicating with a processing device, the memory module configured such that following reception of a command and upon encountering an error condition while processing the command, limiting a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time to indicate an occurrence of the error condition;

wherein the command is indicative of usage of toner or ink in a consumable item for an imaging device and instructs the memory module to punch out at least one memory cell in at least one specified bit field within the memory module indicative of the usage of toner or ink, following reception of the command, the memory module processes the at least one command.

18. The memory module of claim 17, wherein the memory module processes the command by changing the at least one cell from an erased state to a programmed state.

19. The memory module of claim 17, further comprising at least one resistor coupled between the first signal line and a ground potential, the memory module causing current to pass through the at least one resistor for limiting a voltage on the first signal line to be no more than the intermediate voltage.

20. The memory module of claim 19, wherein the intermediate voltage is based at least in part upon a resistance of the at least one resistor.

21. The memory module of claim 17, further comprising at least one diode coupled between the first signal line and a ground potential, the memory module causing current to pass through the at least one diode for limiting a voltage on the first signal line to be no more than the intermediate voltage.

22. The memory module of claim 17, further comprising at least one electrical component coupled between the first signal line and a ground potential, the memory module causing current to pass through the at least one electrical component for limiting a voltage on the first signal line to be no more than the intermediate voltage.

23. The memory module of claim 17, wherein the plurality of signal lines includes a second signal line, and wherein following reception of the command, the memory module limits a voltage on the second signal line to be no greater than a second intermediate voltage between the voltages corresponding to the logic zero state and the voltages corresponding to the logic one state for a period of time to indicate a busy condition.

24. The memory module of claim 23, wherein the second intermediate voltage is substantially the same as the first intermediate voltage.

25. The memory module of claim 23, wherein the memory module receives on the second signal line a second input signal.

26. The memory module of claim 25, wherein the second input signal comprises a clock input signal.

27. The memory module of claim 23, further comprising at least one resistor coupled between the second signal line and a ground potential, the memory module causing current to pass through the at least one resistor for limiting a voltage on the second signal line to be no more than the second intermediate voltage.

28. The memory module of claim 23, further comprising at least one diode coupled between the second signal line and a ground potential, the memory module causing current to pass through the at least one diode for limiting a voltage on the second signal line to be no more than the second intermediate voltage.

29. The memory module of claim 23, further comprising at least one electrical component coupled between the second signal line and a ground potential, the memory module causing current to pass through the at least one electrical component for limiting the voltage on the second signal line to be no more than the second intermediate voltage.

30. A memory module, comprising:

memory cells for storing information therein; and

a plurality of signal lines for communicating with a processing device, the memory module configured such that following reception of a command on the signal lines and during processing thereof, a voltage on a first signal line of the plurality of signal lines is limited for a period of time by the memory module to be no more than an intermediate voltage greater than voltages corresponding to a binary zero value and less than voltages corresponding to a binary one value, for indicating by the memory module one of a busy condition and an error condition;

wherein the command pertains to usage of toner or ink in a consumable item for an imaging device for instructing the memory module to punch out at least one bit of at least one specified bit field within the memory module to indicate the usage of toner or ink, and wherein the memory module processes the command following the reception thereof.

31. The memory module of claim 30, wherein the memory module receives on the first signal line a first input signal.

32. The memory module of claim 30, further comprising at least one electrical component coupled between the first signal line and a ground potential such that the memory module passes current through the at least one electrical component for limiting the voltage on the first signal line to be no more than the intermediate voltage.

33. The memory module of claim 32, wherein the intermediate voltage is based at least in part upon a resistance corresponding to the at least one electrical component.

34. The memory module of claim 30, further comprising at least one diode coupled between the first signal line and a ground potential such that the memory module passes current through the at least one diode for limiting the voltage on the first signal line to be no more than the intermediate voltage.

35. The memory module of claim 30, wherein the plurality of signal lines includes a second signal line, and wherein the memory module is configured such that following reception of the command and during processing thereof, a voltage on the second signal line is limited for a second period of time by the memory module to be no more than a second intermediate voltage greater than the voltages corresponding to the binary zero value and less than the voltages corresponding to the binary one value, for indicating one of the busy condition and the error condition not indicated on the first signal line.

36. The memory module of claim 35, wherein the second intermediate voltage is substantially the same as the first intermediate voltage.

37. The memory module of claim 30, wherein the at least one bit comprises a single bit.