Exchanging data between memory controllers

• US 8,972,667 B2
• Filed: 06/27/2012
• Issued: 03/03/2015
• Est. Priority Date: 06/28/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Auernhammer, Florian Alexander, Caparros Cabezas, Victoria, Doering, Andreas Christian, Sagmeister, Patricia Maria
• Primary Examiner(s): CHOE, YONG J
• Application Number:
  US13/534,063
• Publication Number:
  US 20130007375A1
• Time in Patent Office: 979 Days
• Field of Search: 711/141, 711/154, 711/162, 711/E12.026, 711/E12.103
• US Class Current: 711/141
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1657 Access to multiple memories

Abstract

A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.

Claims

1. A device for exchanging data, comprising:

a plurality of memory controllers, wherein each memory controller of said plurality of memory controllers is coupled to an allocated memory for storing data; and

an interconnect for connecting said plurality of memory controllers,

wherein each memory controller of said plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over said interconnect, wherein each accelerator of said plurality of accelerators is configured to carry out a plurality of concurrent deterministic operations for at least one of;

marking phases of garbage collection in said allocated memory, copying data stored in said allocated memory, replicating data structures stored in said allocated memory, filling memory blocks in said allocated memory, and erasing memory blocks in said allocated memory; and

wherein each accelerator of said plurality of accelerators has a set of registers for carrying out said concurrent deterministic operations.

2. The device according to claim 1, wherein said interconnect is embodied as a ring for connecting said plurality of memory controllers in a ring structure.

3. The device according to claim 1, further comprising:

a plurality of processors, wherein each processor of said plurality of processors is coupled between at least two memory controllers of said plurality of memory controllers.

4. The device according to claim 3, wherein at least one processor of said plurality of processors has an acceleration access unit, wherein said acceleration access unit is configured to carry out a cache coherency protocol with said accelerators of said plurality of memory controllers.

5. The device according to claim 1, wherein each accelerator of said plurality of accelerators is configured to carry out deterministic operations on data.

6. The device according to claim 1, wherein said set of registers includes at least one address register for storing memory addresses of said allocated memories and at least one state register for storing states of said allocated memories.

7. The device according to claim 6, wherein said set of registers further comprises at least one result and error register for managing said concurrent deterministic operations.

8. The device according to claim 6, wherein said set of registers further comprises at least one counter register for managing at least one of said deterministic operations for filling memory blocks and said deterministic operations for erasing memory blocks.

9. The device according to claim 6, wherein said set of registers further comprises at least one completion register for managing a number of completion indications, wherein each completion indication of said number of completion indications indicates a completion of a certain deterministic operation.

10. The device according to claim 6, wherein said set of registers further comprises:

a tag register for managing a number of deterministic operations by a number of tags, wherein said tags are configured to determine operation slots for said number of deterministic operations.

11. The device according to claim 10, wherein said set of registers further comprises at least one bypass register for bypassing the said register such that a number of predefined deterministic operations are prioritized compared to said number of deterministic operations being managed by said tag register.

12. The device according to claim 1,

wherein each memory controller of said plurality of memory controllers has an interface for interfacing said interconnect;

and

wherein said interface comprises a buffer for preventing a deadlock between said concurrent deterministic operations.

13. The device according to claim 1, further comprising:

an I/O switch connected to said interconnect, wherein said I/O switch is connected to a number of I/O devices such that said number of I/O devices is adapted to directly access said memory controllers over said interconnect.