Gold die bond sheet preform

• US 8,975,176 B2
• Filed: 03/12/2014
• Issued: 03/10/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Materion Corporation
• Original Assignee: Materion Corporation
• Inventors: Kothandapani, Ramesh
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US14/205,403
• Publication Number:
  US 20140264949A1
• Time in Patent Office: 363 Days
• Field of Search: 257/E23.02, 257/E23.023, 257/E23.04, 257/503, 257781-786, 257/778, 438/117, 438/118, 438/121, 438/612, 438/614, 438/666
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/2711 Shaping
• CPC Class Codes: H01L 2224/27334 using preformed layer
• CPC Class Codes: H01L 2224/2746 Plating
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/32013 the layer connector being larger than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83444 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/83447 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/83815 Reflow soldering
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 24/27 Manufacturing methods
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]

Abstract

The amount of gold required for bonding a semiconductor die to an electronic package is reduced by using a sheet preform tack welded to the package prior to mounting the die. The preform, only slightly larger than a semiconductor die to be attached to the package, is placed in the die bond location and tack welded to the package at two spaced locations.

Claims

1. A method of forming a semiconductor bond site on a semiconductor package comprising the steps of:

forming a gold containing die bond sheet preform having a width, a length and a substantially uniform thickness;

placing the die bond sheet preform on a die bond area on a semiconductor package; and

welding the die bond sheet preform to the package die bond area at two spaced apart spots, the two spaced apart spots having a total area significantly smaller than the area of the sheet preform.

2. The method of claim 1 wherein the die bond sheet preform contains gold and tin.

3. The method of claim 1 wherein the die bond sheet preform is about 0.0005 inch thick.

4. The method of claim 3, wherein the die bond sheet preform is rolled to a final thickness.

5. The method of claim 1 wherein the die bond sheet preform is welded to the package die bond area with an electric current resistance welding using a welding current waveform having only one principal current peak.

6. The method of claim 1, wherein the welding the die bond sheet preform to the package die bond area includes using a working electrode contact area of approximately 6.2 mm×

2.39 mm.

7. The method of claim 1, further comprising placing a die on the die bond sheet preform.

8. The method of claim 7, further comprising attaching the die to the package die bond area by at least partially liquefying the die bond sheet preform.

9. The method claim 7, wherein the die bond sheet preform is slightly larger than a footprint of the die.

10. The method of claim 1, wherein the total area of the spot welds is approximately 0.3 mm to 0.5 mm.

11. A semiconductor package comprising a copper tungsten base having a die bond site and a die bond sheet preform containing gold and tin welded to the base die bond site in at least two locations spaced from one another.

12. The semiconductor package of claim 11, wherein the die bond sheet preform is a preform having a thickness of about 0.0005 inch.

13. The semiconductor package of claim 11, wherein the die bond sheet preform is spot welded to the base die bond site.

14. The semiconductor package of claim 13, wherein the at least two location comprise welds having an area of approximately 0.3 mm to 0.5 mm.

15. A semiconductor package formed by:

forming a gold containing die bond sheet preform having a width, a length and a substantially uniform thickness;

placing the die bond sheet preform on a die bond area on a semiconductor package;

welding the die bond sheet preform to the package die bond area at two spaced apart spots, the two spaced apart spots having a total area significantly smaller than the area of the sheet preform.

16. The semiconductor package of claim 15, wherein the die bond sheet preform is about 0.0005 inch thick.

17. The semiconductor package of claim 15, wherein the die bond sheet preform is rolled to a final thickness.

18. The semiconductor package of claim 15, wherein the die bond sheet preform is welded to the die bond area with an electric current resistance welding using a welding current waveform having only one principal current peak.

19. The semiconductor package of claim 15, wherein the die bond sheet preform is spot welded to the die bond area.

20. The semiconductor package of claim 19, wherein the at least two spots comprise welds having an area of approximately 6.2 mm×

2.39 mm.