Integrated device incorporating low-voltage components and power components, and process for manufacturing such device

• US 8,975,723 B2
• Filed: 07/20/2010
• Issued: 03/10/2015
• Est. Priority Date: 07/21/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Depetro, Riccardo, Manzini, Stefano
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Roland, Christopher M
• Application Number:
  US12/839,989
• Publication Number:
  US 20110018068A1
• Time in Patent Office: 1,694 Days
• Field of Search: 257/392, 257/500, 257/501, 257/E27.064, 438/221, 438/275
• US Class Current: 257/501
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, coupled to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.

Claims

1. Integrated device comprising:

a semiconductor body having a depressed first portion and second portions projecting from the first portion;

an STI insulation structure, extending on the first portion of the semiconductor body, having a first sidewall with the second portions of the semiconductor body, the first sidewall disposed at a first angle with respect to a plane defined by a top surface of the second portion that is less than ninety degrees, having an aperture exposing part of the first portion, the aperture having sidewalls disposed at a second angle with respect to the plane defined by the to surface of the second portion that is less than ninety degrees and having a face adjacent to a surface of the first portion of the semiconductor body, the second angle less than the first angle by at least 10 degrees;

low-voltage CMOS components, accommodated in the second portions, in a first region of the semiconductor body; and

a power component, in a second region of the semiconductor body;

wherein the power component comprises at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, connected to the conduction region and crossing the STI insulation structure perpendicularly to the plane defined by the to surface of the second portion of the semiconductor body.

2. Device according to claim 1, wherein the conduction region is formed below the STI insulation structure.

3. Device according to claim 1, wherein the STI insulation structure aperture is crossed by the conduction contact.

4. Device according to claim 3, wherein the sidewalls of the aperture have a slope comprised between 20°

and 70°

.

5. Device according to claim 1, wherein the conduction region is a source region.

6. Device according to claim 5, comprising a body region, formed in the first portion of the semiconductor body and accommodating the conduction region.

7. Device according to claim 6, comprising a gate region, arranged in part in the aperture extending above a junction region of the semiconductor body adjacent to the body region, above a channel region defined by a portion of the body region comprised between the junction region and the conduction region, and above part of the conduction region.

8. Device according to claim 7, wherein the gate region extends in part above the STI insulation structure.

9. Device according to claim 1, wherein the semiconductor body comprises at least a third portion projecting from the first portion, laterally delimited by the STI insulation structure and selectively connectable to the conduction region, and wherein the power component comprises a further conduction contact, connected to the third portion of the semiconductor body.

10. Device according to claim 1, wherein the power component comprises a further conduction contact, connected to the first portion of the semiconductor body and crossing the STI insulation structure perpendicularly to the plane defined by the to surface of the second portion of the semiconductor body.

11. A semiconductor structure, comprising:

a semiconductor region;

a first source region disposed on a first surface at a first level of the semiconductor region and bounded by a first structure at a boundary having a first face disposed at a first angle with respect to a plane defined by the first level of the semiconductor region, the first angle less than ninety degrees; and

a second source region disposed on a second surface at a second level of the semiconductor region below the first level and formed in a source window exposing the second surface and bounded by a second structure at a first boundary having a second face disposed at a second angle with respect to a plane defined by the second level of the semiconductor region, the second angle less than the first angle by at least 10 degrees, said second structure including a second boundary having a third face disposed at the first angle.

12. The semiconductor structure of claim 11 wherein the semiconductor region comprises a substrate.

13. The semiconductor structure of claim 11 wherein the semiconductor region comprises an epitaxial region.

14. The semiconductor structure of claim 11 wherein:

the first source region is disposed contiguous with the first surface; and

the second source region is disposed contiguous with the second surface.

15. The semiconductor structure of claim 11, further comprising:

a lower power transistor that includes the first source region; and

a higher power transistor that includes the second source region.

16. The semiconductor structure of claim 11, further comprising:

a first isolation region disposed in the semiconductor region at substantially the first level to form the first structure; and

a second isolation region disposed in the semiconductor region at substantially the first level to form the second structure.

17. The semiconductor structure of claim 11, further comprising:

a first isolation region disposed in the semiconductor region at substantially the first level to form the first structure and having a sidewall defined by the first face; and

a second isolation region disposed in the semiconductor region at the substantially the first level to form the second structure and having a sidewall defined by the second face.

18. The semiconductor structure of claim 11, further comprising:

a first isolation region disposed in the semiconductor region substantially at the first level to form the first structure and having a sidewall defined by the first face; and

a second isolation region disposed in the semiconductor region substantially at the first level to form the second structure and having a sidewall defined by the third face.

19. The semiconductor structure of claim 11, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region at substantially the first level; and

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region at substantially the first level.

20. The semiconductor structure of claim 11, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level; and

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the first level.

21. The semiconductor structure of claim 11, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region at substantially the first level; and

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region at substantially the second level.

22. The semiconductor structure of claim 11, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level; and

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second level.

23. The semiconductor structure of claim 11, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level;

a first isolation region disposed in the semiconductor region substantially at the first level to form the first structure and having a sidewall with a slope defining the first face;

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the first level; and

a second isolation region disposed in the semiconductor region substantially at the first level to form the second structure and having a sidewall with a slope defining the third face.

24. The semiconductor structure of claim 11, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level;

a first isolation region disposed in the semiconductor region substantially at the first level to form the first structure and having a sidewall with a slope defining the first face;

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second level; and

a second isolation region disposed in the semiconductor region substantially at the first level to form the second structure and having a sidewall with a slope defining the second face.

25. The semiconductor structure of claim 11, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level;

a first isolation region disposed in the semiconductor region substantially at the first level to form the first structure and having a sidewall with a slope defining the first face;

a higher power transistor that includes the second source region and that includes a second drain region disposed in the semiconductor region and having at least a portion at substantially the first level; and

a second isolation region disposed in the semiconductor region substantially at the first level to form the second structure and having a first sidewall with a slope defining the second face and having a second sidewall with a slope defining the third face.

26. The semiconductor structure of claim 11, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level;

a first isolation region disposed in the semiconductor region substantially at the first level to form the first structure and having a sidewall with a slope defining the first face;

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second level; and

a second isolation region disposed in the semiconductor region substantially at the first level to form the second structure and having a first sidewall with a slope defining the second face and having a second sidewall with a slope defining the third face.

27. An integrated circuit, comprising:

a die having a surface and a semiconductor layer disposed below the surface;

a first source region disposed in the semiconductor layer at a first distance from the surface; and

a second source region disposed in the semiconductor layer at a second distance from the surface, wherein a source window for the second source region is surrounded by a first isolation region having a first sidewall disposed at a first slope greater than a second slope of a second sidewall of the first isolation region, the first slope greater than the second slope by a factor of at least 10%, wherein the first slope and the second slope are less than ninety degrees.

28. The integrated circuit of claim 27, further comprising:

a lower power transistor that includes the first source region; and

a higher power transistor that includes the second source region.

29. The integrated circuit of claim 27, further comprising:

the first isolation region disposed in the semiconductor layer at substantially the first distance from the surface and surrounding the source window; and

a second isolation region disposed in the semiconductor layer at substantially the first distance from the surface and surrounding an active area within which the first source region is formed.

30. The integrated circuit of claim 27, further comprising:

the first isolation region disposed in the semiconductor layer at substantially the first distance from the surface such that the second sidewall is contiguous with the source window; and

a second isolation region disposed in the semiconductor layer at substantially the first distance from the surface contiguous with an active area within which the first source region.

31. The integrated circuit of claim 27, further comprising:

the first isolation region disposed in the semiconductor layer substantially at the first distance from the surface and having the second sidewall adjacent to the source window; and

a second isolation region disposed in the semiconductor layer substantially at the first distance from the surface and having the first sidewall;

each of the sidewalls having a different slope.

32. The integrated circuit of claim 27, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface; and

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface.

33. The integrated circuit of claim 27, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface; and

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second distance from the surface.

34. The integrated circuit of claim 27, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface;

the first isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a sidewall with a slope having a first magnitude;

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second distance from the surface; and

a second isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a sidewall with a slope having a second magnitude.

35. The integrated circuit of claim 27, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface;

the first isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a sidewall having a slope with a first magnitude;

a higher power transistor that includes the second source region and that includes a second drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface; and

a second isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a first sidewall with a slope having a second magnitude and having a second sidewall with a slope having substantially the first magnitude.

36. The integrated circuit of claim 33, further comprising:

a lower power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface;

the first isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a sidewall with a slope having a first magnitude;

a higher power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second distance from the surface; and

a second isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a first sidewall with a slope having a second magnitude and having a second sidewall with a slope having substantially the second magnitude.

37. A system, comprising:

a first integrated circuit, including;

a die having a surface and a semiconductor layer disposed below the surface;

a first source region disposed in the semiconductor layer at a first distance from the surface; and

a second source region disposed in the semiconductor layer at a second distance from the surface, wherein a source window for the second source region is surrounded by a first insulation region having a first side wall disposed at a first angle with respect to a surface of the second source region, the first angle different from a second angle with respect to a surface of the second source region of a second side wall of the first insulation region, wherein the difference is at least 10 degrees; and

a second integrated circuit coupled to the first integrated circuit.

38. The system of claim 37 wherein the first and second integrated circuits are disposed on a same die.

39. The system of claim 37 wherein the first and second integrated circuits are disposed on respective dies.

40. The system of claim 37 wherein at least one of the first and second integrated circuits comprises a controller.