Semiconductor device and method of manufacturing the same

• US 8,975,732 B2
• Filed: 03/13/2013
• Issued: 03/10/2015
• Est. Priority Date: 03/14/2012
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tojo, Akira, Higuchi, Kazuhito, Iguchi, Tomohiro, Sasaki, Akihiro, Uchida, Masayuki, Fukumitsu, Masako, Hiratsuka, Daisuke
• Primary Examiner(s): Trinh, Michael
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US13/799,218
• Publication Number:
  US 20130241040A1
• Time in Patent Office: 727 Days
• Field of Search: 257/666
• US Class Current: 257/666
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/051 another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

According to one embodiment, a semiconductor device includes, a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side, an electrically conductive frame provided on a side periphery of the chip, a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip, and an insulation side portion provided between the electrically conductive frame and the side periphery of the chip.

Claims

1. A semiconductor device comprising:

a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on an other side;

an electrically conductive frame provided on a side periphery of the chip;

a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip; and

an insulation side portion provided between the electrically conductive frame and the side periphery of the chip,

wherein an electrical connection from the one side to the second chip electrode is enabled via the electrically conductive frame and the rewiring.

2. The semiconductor device of claim 1, wherein

the semiconductor device is configured as a semiconductor package device,

a third chip electrode is formed on the second surface of the chip, and

the semiconductor package device includes:

a rewiring configured to electrically connect the third chip electrode and the electrically conductive frame on the other side of the chip; and

an insulation portion provided between a rewiring of the second chip electrode and a rewiring of the third chip electrode,

each of the first to third chip electrodes is any one of a source, a gate and a drain, and

an electrical connection to the first to third chip electrodes is enabled from the one side.

3. The semiconductor device of claim 1, wherein the rewiring is formed of a plating film.

4. The semiconductor device of claim 1, wherein the first chip electrode and a part on one side of the electrically conductive frame constitute an external electrode.

5. The semiconductor device of claim 1, further comprising:

a third chip electrode is formed on the first surface of the chip, wherein

an insulation portion is formed between the first chip electrode and the third chip electrode.

6. The semiconductor device of claim 1, wherein the rewiring is directly connected to the insulation side portion.

7. A semiconductor device comprising:

a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on an other side;

an electrically conductive frame provided on a side periphery of the chip;

a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip;

an insulation side portion provided between the electrically conductive frame and the side periphery of the chip;

a first rewiring electrode which is electrically connected to the first chip electrode on the one side of the chip and constitutes a first external electrode;

a second rewiring electrode which is electrically connected to the electrically conductive frame on the one side of the chip and constitutes a second external electrode; and

an electrode insulation portion configured to mutually insulate a plurality of said rewiring electrodes on the one side of the chip,

wherein an electrical connection to the first chip electrode is enabled from the one side via the first rewiring electrode, and

an electrical connection to the second chip electrode is enabled from the one side via the second rewiring electrode, the electrically conductive frame and the rewiring.

8. The semiconductor device of claim 7, wherein at least any one of the rewiring and the rewiring electrodes includes at least two layers, and at least one of the at least two layers includes a seed layer which becomes an adhesive layer.

9. The semiconductor device of claim 7, wherein an insulation film is formed on at least either a part of the first surface on the one side, which avoids the rewiring electrodes, or the second surface on the other side.

10. A semiconductor device comprising:

a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on an other side;

an electrically conductive frame provided on a side periphery of the chip;

a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip; and

an insulation side portion provided between the electrically conductive frame and the side periphery of the chip, wherein

the semiconductor device is configured as a semiconductor package device,

a third chip electrode is formed on the first surface of the chip,

the semiconductor package device includes a rewiring electrode which is electrically connected to the third chip electrode on the one side of the chip and constitutes an external electrode,

each of the first to third chip electrodes is any one of a source, a gate and a drain, and

an electrical connection to the first to third chip electrodes is enabled from the one side.

11. The semiconductor device of claim 10, wherein

the electrically conductive frame includes a first frame portion which is connected to the second chip electrode via the rewiring, and a second frame portion which is connected to the third chip electrode via the rewiring, and

the first frame portion and the second frame portion are insulated from each other.

12. A semiconductor device comprising:

a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on an other side;

an electrically conductive frame provided on a side periphery of the chip;

a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip; and

an insulation side portion provided between the electrically conductive frame and the side periphery of the chip, wherein

an electrically conductor member, which is electrically connected to the second chip electrode, is provided on the second surface on the other side of the chip,

the rewiring is formed on a surface on an other side of the electrically conductive member, and

the electrically conductive frame and the rewiring are electrically connected via the electrically conductive member.