Amplifiers with improved isolation

• US 8,975,968 B2
• Filed: 01/25/2013
• Issued: 03/10/2015
• Est. Priority Date: 01/25/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Abdelhalem, Sherif, Biederman, William James III
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US13/750,878
• Publication Number:
  US 20140210554A1
• Time in Patent Office: 774 Days
• Field of Search: 330/277, 330/283, 330/311
• US Class Current: 330/311
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/426 the amplifier comprising circuitry for protection against overload
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/21142 Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 2203/7206 the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias voltage in the amplifier
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/22 with tubes only H03F3/24 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

Amplifiers with improved isolation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier having a gain transistor, first and second cascode transistors, and a shunt transistor. The gain transistor receives an input signal and provides an amplified signal. The first cascode transistor is coupled between the gain transistor and an intermediate node and receives the amplified signal. The second cascode transistor is coupled between the intermediate node and an output node and provides an output signal. The shunt transistor is coupled between the intermediate node and circuit ground. The first and second cascode transistors are enabled to provide the output signal. The shunt transistor is (i) disabled when the cascode transistors are enabled and (ii) enabled to short the intermediate node to circuit ground when the cascode transistors are disabled.

Claims

1. An apparatus comprising:

a gain transistor configured to receive an input signal and to provide an amplified signal;

a first cascode transistor coupled between the gain transistor and an intermediate node, the first cascode transistor having a first gate and configured to be enabled based on a bias voltage received at the first gate;

a second cascode transistor coupled between the intermediate node and an output node, the second cascode transistor having a second gate that is coupled to the first gate, the second cascode transistor configured to be enabled based on receiving the bias voltage at the second gate and configured to provide an output signal; and

a shunt transistor coupled between the intermediate node and ground.

2. The apparatus of claim 1, further comprising:

a third cascode transistor coupled between the gain transistor and a second intermediate node;

a fourth cascode transistor coupled between the second intermediate node and a second output node, the fourth cascode transistor configured to provide a second output signal; and

a second shunt transistor coupled between the second intermediate node and ground.

3. The apparatus of claim 1, wherein the first cascode transistor, the second cascode transistor, and the shunt transistor comprise a first cascode circuit, the apparatus further comprising:

a second gain transistor configured to receive the input signal and to provide a second amplified signal; and

a second cascode circuit coupled between the second gain transistor and a second output node, the second cascode circuit configured to provide a second output signal.

4. The apparatus of claim 3, further comprising:

a third cascode circuit coupled between the gain transistor and the second output node, a fourth cascode circuit coupled between the second gain transistor and the output node, or a combination thereof.

5. The apparatus of claim 1, wherein the first cascode transistor, the second cascode transistor, and the shunt transistor comprise a first cascode circuit, the apparatus further comprising:

a second gain transistor configured to receive a second input signal and to provide a second amplified signal; and

a second cascode circuit coupled between the second gain transistor and a second output node, the second cascode circuit configured to provide a second output signal.

6. The apparatus of claim 5 further comprising:

a third cascode circuit coupled between the gain transistor and the second output node; and

a fourth cascode circuit coupled between the second gain transistor and the output node.

7. The apparatus of claim 6, further comprising:

a third gain transistor configured to receive the input signal and to provide a third amplified signal;

a fifth cascode circuit coupled between the third gain transistor and the output node; and

a sixth cascode circuit coupled between the third gain transistor and the second output node.

8. The apparatus of claim 7, further comprising:

a fourth gain transistor configured to receive the second input signal and to provide a fourth amplified signal;

a seventh cascode circuit coupled between the fourth gain transistor and the output node; and

an eighth cascode circuit coupled between the fourth gain transistor and the second output node.

9. The apparatus of claim 1, wherein the first cascode transistor has a first length and the second cascode transistor has a second length, and wherein the first length and the second length are selected based on at least one target operating characteristic of the first cascode transistor and the second cascode transistor.

10. The apparatus of claim 9, wherein the first length and the second length are the same length.

11. The apparatus of claim 1, further comprising a cascode circuit coupled between the gain transistor and a second output node, the cascode circuit configured to provide a second output signal.

12. The apparatus of claim 11, wherein the cascade circuit comprises:

a third cascade transistor coupled between the gain transistor and a second intermediate node; and

a second shunt transistor coupled between the second intermediate node and ground.

13. A method comprising:

amplifying an input signal via a gain transistor to provide an amplified signal;

buffering the amplified signal based on a first operating mode via a first cascode transistor coupled to an intermediate node and a second cascode transistor coupled to the intermediate node to provide an output signal, wherein, during the first operating mode, the first cascode transistor is enabled, a shunt transistor is disabled, and the second cascode transistor is enabled and provides the output signal; and

shorting the intermediate node to ground via the shunt transistor based on a second operating mode.

14. The method of claim 13, further comprising:

buffering the amplified signal via a third cascode transistor and a fourth cascode transistor to provide a second output signal when the third cascode transistor and the fourth cascode transistor are enabled, the third cascode transistor and the fourth cascode transistor coupled to a second intermediate node; and

shorting the second intermediate node to ground via a second shunt transistor when the third cascode transistor and the fourth cascode transistor are disabled.

15. The method of claim 13, further comprising:

amplifying the input signal via a second gain transistor to provide a second amplified signal;

buffering the second amplified signal via a third cascode transistor and a fourth cascode transistor to provide a second output signal when the third cascode transistor and the fourth cascode transistor are enabled, the third cascode transistor and the fourth cascode transistor coupled to a second intermediate node; and

shorting the second intermediate node to ground via a second shunt transistor when the third cascode transistor and the fourth cascode transistor are disabled.

16. The method of claim 13, further comprising:

amplifying a second input signal via a second gain transistor to provide a second amplified signal;

buffering the second amplified signal with third cascode transistor and a fourth cascode transistor to provide a second output signal when the third cascode transistor and the fourth cascode transistor are enabled, the third cascode transistor and the fourth cascode transistor coupled to a second intermediate node; and

shorting the second intermediate node to ground via a second shunt transistor when the third cascode transistor and the fourth cascode transistor are disabled.

17. The method of claim 13, wherein, during the second operating mode, the first cascode transistor and the second cascode transistor are disabled and the shunt transistor is enabled.

18. An apparatus comprising:

means for providing an amplified signal based on an input signal;

first means for buffering the amplified signal, the first means for buffering coupled between the means for providing the amplified signal and an intermediate node the first means for buffering configured to be enabled based on a bias voltage received at a first gate;

second means for buffering the amplified signal, the second means for buffering coupled between the intermediate node and an output node and configured to be enabled based on the bias voltage received at a second gate that is coupled to the first gate; and

means for shorting the intermediate node to ground.

19. The apparatus of claim 18, further comprising:

third means for buffering the amplified signal, the third means for buffering coupled between the means for providing the amplified signal and a second intermediate node;

fourth means for buffering the amplified signal, the fourth means for buffering coupled between the second intermediate node and a second output node, the fourth means for buffering configured to provide a second output signal; and

means for shorting the second intermediate node to ground.

20. The apparatus of claim 18, further comprising:

second means for providing a second amplified signal based on a second input signal;

third means for buffering the second amplified signed, the third means for buffering coupled between the second means for providing the second amplified signal and a second intermediate node;

fourth means for buffering the second amplified signal, the fourth means for buffering coupled between the second intermediate node and a second output node, the fourth means for buffering configured to provide a second output signal; and

means for shorting the second intermediate node to ground.