Methods and devices for voltage reduction for active matrix displays using variability of pixel device capacitance

• US 8,988,409 B2
• Filed: 07/22/2011
• Issued: 03/24/2015
• Est. Priority Date: 07/22/2011
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Govil, Alok
• Primary Examiner(s): Abdulselam, Abbas
• Assistant Examiner(s): OLIVER, GERALD L
• Application Number:
  US13/189,428
• Publication Number:
  US 20130021313A1
• Time in Patent Office: 1,341 Days
• Field of Search: 345211-215
• US Class Current: 345/212
• CPC Class Codes: G02B 26/00 Optical devices or arrangements for the control of light using movable or deformable optical elements control of light by modification of the optical properties of the media of the elements involved therein G02F1/00
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 3/3466 based on interferometric effect

Abstract

Methods and devices for reducing the voltage required to update an array of display elements having variable capacitance are described herein. In one implementation, the method includes driving a display element to a first state using a reset drive line. The method further includes driving the display element to a second state using a column drive line. The capacitance of the display element is higher in the first state than in the second state.

Claims

1. An apparatus comprising:

at least one display element having a plurality of display states, each of the display states corresponding to one of a plurality of charge levels applied to the at least one display element, the plurality of display states including a least a first higher capacitance display state and a second display state, wherein the capacitance of the display element is higher in the first higher capacitance display state than in the second display state;

a drive switch coupling the at least one display element to a drive voltage line when addressed by a drive address line; and

a reset switch coupling the at least one display element to a reset voltage line when addressed by a reset address line;

wherein the reset voltage line is configured to set the at least one display element to the first higher capacitance display state when coupled to the at least one display element.

2. The apparatus of claim 1, wherein the drive voltage line is coupled to one or more columns of display elements.

3. The apparatus of claim 2, wherein the drive address line is coupled to one or more rows of display elements.

4. The apparatus of claim 3, further including an address line driver selectively coupled to one or both of the drive address line and the reset address line.

5. The apparatus of claim 4, wherein the at least one display element includes a bistable display element.

6. The apparatus of claim 5, wherein the bistable display element includes an interferometric modulator.

7. The apparatus of claim 1, wherein the first higher capacitance display state has a capacitance of five or more times the capacitance of the second display state.

8. The apparatus of claim 1, wherein the first higher capacitance display state has a capacitance of ten or more times the capacitance of the second display state.

9. A method of updating an array including at least one display element, the method comprising:

coupling the at least one display element to a reset voltage line, the at least one display element having at least a first and a second display state, wherein the capacitance of the at least one display element is higher in the first higher capacitance display state than in the second display state;

setting the at least one display element to the first higher capacitance display state;

decoupling the at least one display element from the reset voltage line;

coupling the at least one display element to a drive voltage line; and

driving the at least one display element to the second display state.

10. The method of claim 9, wherein the array includes one or more rows of display elements and one or more columns of display elements, wherein each of the one or more columns of display elements is associated with a respective drive voltage line, and wherein each display element in each of the one or more rows of display elements is selectively coupled to its respective drive voltage line by a respective drive address line.

11. The method of claim 10, wherein each of the one or more rows of display elements is associated with a respective reset voltage line, and wherein each display element in each of the one or more rows of display elements is selectively coupled to its respective reset voltage line by a respective reset address line.

12. The method of claim 11, wherein coupling the at least one display element to the drive voltage line includes coupling only the display elements of one row to their respective drive voltage lines at one time.

13. The method of claim 12, wherein coupling the at least one display element to a reset voltage line includes coupling the display elements of a first row to their respective reset voltage lines while coupling the display elements of a second row to their respective drive voltage lines.

14. The method of claim 9, wherein the at least one display element includes a bistable display element.

15. The method of claim 14, wherein the bistable display element includes an interferometric modulator.

16. A method of updating an array including at least one row of display elements, the method comprising:

pre-charging at least one row of display elements with a reset voltage, the display elements of the at least one row having at least a first and a second display state, wherein the capacitance of the display elements of the at least one row is higher in the first higher capacitance display state than in the second display state;

waiting for at least some of the display elements in the at least one row of display elements to reach the first higher capacitance display state;

charging the at least one row of display elements with a drive voltage; and

waiting for at least some of the display elements in the at least one row of display elements to reach the second display state.

17. The method of claim 16, wherein the at least one row of display elements includes one or more bistable display element.

18. The apparatus of claim 17, wherein the one or more bistable display elements include interferometric modulators.

19. An apparatus comprising:

at least one display element having a plurality of display states, each of the display states corresponding to one of a plurality of charge levels applied to the at least one display element, the plurality of display states including a least a first higher capacitance display state and a second display state, wherein the capacitance of the display element is higher in the first higher capacitance display state than in the second display state;

means for coupling the at least one display element to a drive voltage line when addressed by a drive address line;

means for coupling the at least one display element to a reset voltage line; and

means for setting the at least one display element to the first higher capacitance display state.

20. The apparatus of claim 19, wherein the apparatus includes an array of one or more rows of display elements and one or more columns of display elements, wherein each of the one or more columns of display elements is associated with a respective drive voltage line, and wherein each display element in each of the one or more rows of display elements is selectively coupled to its respective drive voltage line by a respective drive address line.

21. The apparatus of claim 20, wherein each of the one or more rows of display elements is associated with a respective reset voltage line, and wherein each display element in each of the one or more rows of display elements is selectively coupled to its respective reset voltage line by a respective reset address line.

22. The apparatus of claim 21, wherein the means for coupling the at least one display element to the drive voltage line includes means for coupling only the display elements of one row to their respective drive voltage lines at one time.

23. The apparatus of claim 22, wherein the means for coupling the at least one display element to a reset voltage line includes means for coupling the display elements of a first row to their respective reset voltage lines while coupling the display elements of a second row to their respective drive voltage lines.

24. The apparatus of claim 19, wherein the at least one display element includes a bistable display element.

25. The apparatus of claim 24, wherein the bistable display element includes an interferometric modulator.

26. The apparatus of claim 19, further comprising:

a display;

a processor that is configured to communicate with said display, said processor being configured to process image data; and

a memory device that is configured to communicate with said processor.

27. The apparatus as recited in claim 26, further comprising:

a driver circuit configured to send at least one signal to said display; and

a controller configured to send at least a portion of said image data to said driver circuit.

28. The apparatus as recited in claim 26, further comprising:

an image source module configured to send said image data to said processor.

29. The apparatus as recited in claim 28, wherein said image source module includes at least one of a receiver, transceiver, and transmitter.

30. The apparatus as recited in claim 26, further comprising:

an input device configured to receive input data and to communicate said input data to said processor.

31. The apparatus of claim 19, wherein the first higher capacitance display state has a capacitance of five or more times the capacitance of the second display state.

32. The apparatus of claim 19, wherein the first higher capacitance display state has a capacitance of ten or more times the capacitance of the second display state.