Pipeline method and system for switching packets
First Claim
1. A network device comprising:
- a media access controller (MAC) configured to receive a packet received by the network device;
a first series of elements configured to forward from the media access controller (MAC) to a backplane, the first series of elements comprising a first processor and a first memory, the first processor configured to process the packet and store corresponding packet data in the first memory;
a second series of elements configured to forward data from the backplane to the MAC, the second series of elements comprising a second processor and a second memory; and
a path that enables the packet data to be forwarded from an element in the first series of elements to an element in the second series of elements without using the backplane, wherein the element in the first series of elements is a first application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) and the element in the second series of elements is a second FPGA, wherein the first ASIC or FPGA is different from the second FPGA;
wherein the element in the second series of elements, which receives the packet data forwarded using the path, is configured to;
store the packet data in the second memory; and
notify the second processor after the packet data has been stored in the second memory.
2 Assignments
0 Petitions
Accused Products
Abstract
A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.
548 Citations
18 Claims
-
1. A network device comprising:
-
a media access controller (MAC) configured to receive a packet received by the network device; a first series of elements configured to forward from the media access controller (MAC) to a backplane, the first series of elements comprising a first processor and a first memory, the first processor configured to process the packet and store corresponding packet data in the first memory; a second series of elements configured to forward data from the backplane to the MAC, the second series of elements comprising a second processor and a second memory; and a path that enables the packet data to be forwarded from an element in the first series of elements to an element in the second series of elements without using the backplane, wherein the element in the first series of elements is a first application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) and the element in the second series of elements is a second FPGA, wherein the first ASIC or FPGA is different from the second FPGA; wherein the element in the second series of elements, which receives the packet data forwarded using the path, is configured to; store the packet data in the second memory; and notify the second processor after the packet data has been stored in the second memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 13, 14, 15)
-
-
8. A method comprising:
-
receiving, at a media access controller (MAC) in a network device, a packet received by the network device; providing, in the network device, a first series of elements configured to forward data from the media access controller (MAC) to a backplane of the network device, the first series of elements comprising a first processor and a first memory; providing, in the network device, a second series of elements configured to forward data from the backplane to the MAC, the second series of elements comprising a second processor and a second memory; processing the packet, by the first processor, and storing corresponding packet data in the first memory; forwarding, from an element in the first series of elements to an element in the second series of elements, the packet data without using the backplane, wherein the element in the first series of elements is a first application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) and the element in the second series of elements is a second FPGA, wherein the first ASIC or FPGA is different from the second FPGA; storing, by the element in the second series of elements that receives the packet data, the packet data in the second memory; and notifying, by the element in the second series of elements, the second processor after the packet data has been stored in the second memory. - View Dependent Claims (9, 10, 11, 12, 16, 17, 18)
-
Specification