Contactless technique for evaluating a fabrication of a wafer

• US 8,990,759 B2
• Filed: 06/01/2010
• Issued: 03/24/2015
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Tau-Metrix, Inc.
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Aghababazadeh, Majid, Estabil, Jose J., Pakdaman, Nader, Steinbrueck, Gary L.
• Primary Examiner(s): DOAN, NGHIA M
• Application Number:
  US12/791,665
• Publication Number:
  US 20100304509A1
• Time in Patent Office: 1,757 Days
• Field of Search: 716 51- 52, 716/56, 716/136, 702/127, 702/134, 702/172, 324457-458
• US Class Current: 716/136
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. A method for evaluating fabrication of at least a portion of a wafer, the method comprising:

(a) independently detecting and activating a plurality of test structures distributed at a plurality of locations on the portion of the wafer;

the plurality of test structures being formed during a first fabrication process to establish electrical connectivity for a first set of elements which include the plurality of test structures, each test structure being activated and then detected without electrical or physical connectivity to any circuit elements that are part of a design of the product wafer;

wherein independent detecting and activating is performed immediately after the first fabrication process;

(b) programmatically correlating, with use of one or more computers, an output of one or more of the plurality of test structures to a specified performance parameter that is indicative of an attribute that results from performance of at least one or more fabrication processes for the wafer.

2. The method of claim 1, further comprising correlating the specified performance parameter during a design phase to at least one of the one or more fabrication processes.

3. The method of claim 1, further comprising correlating the specified performance parameter during a design phase to an attribute of a device on either a scribe or on any portion of the die of the product wafer;

wherein the attribute is a result of at least of one or more fabrication processes.

4. The method of claim 3, wherein correlating the specified performance parameter to the attribute of the device on the die includes correlating the specified performance parameter to a gate length or gate width variation of any one or more switching elements on the die;

wherein the gate length or gate width variation is a result of at least one of the one or more fabrication processes.

5. The method of claim 3, wherein correlating the specified performance parameter to the attribute of the device on the die includes correlating the specified performance parameter to a capacitance characteristic on any portion of the die;

wherein the capacitance characteristic is a result of at least one of the one or more fabrication processes.

6. The method of claim 3, wherein correlating the specified performance parameter to the attribute of the device on the die includes correlating the specified performance parameter to a resistivity variation on any portion of the die;

wherein the resistivity variation is expected from performance of fabrication of the product wafer.

7. The method of claim 3, wherein correlating the specified performance parameter to the attribute of the device on the die includes correlating the specified performance parameter to an electrical bias characteristic on any portion of the die, wherein the electrical bias characteristic results from the fabrication of the product wafer.

8. The method of claim 7, wherein the attribute is a result of one or more steps for patterning the product wafer.

9. The method of claim 3, wherein the attribute is a result of one or more steps for etching the product wafer including planarization.

10. The method of claim 3, wherein correlating the specified performance parameter to the attribute of the device on the die includes correlating the specified performance parameter to a resistivity variation of any one or more switching elements on the die;

wherein the resistivity variation is a result of one or more steps or fabricating the wafer.

11. The method of claim 3, wherein correlating the specified performance parameter to the attribute of the device includes correlating the specified performance parameter to a leakage current of a device on the wafer.

12. The method of claim 3, wherein correlating the specified performance parameter to the attribute of the device includes correlating the specified performance parameter to a threshold voltage of a device on the wafer.

13. The method of claim 3, wherein correlating the specified performance parameter to the attribute of the device includes correlating the specified performance parameter to a current of a device on the wafer.

14. The method of claim 1, wherein the attribute corresponds to a variance that results from at least one of the one or more fabrication processes.

15. The method of claim 1, wherein (a) and (b) is performed during a design process for fabricating the wafer.

16. The method of claim 1, wherein (a) and (b) is performed during a test process in the fabrication.

17. The method of claim 1, wherein the one or more fabrication processes includes a manufacturing process for polishing the product wafer.

18. The method of claim 1, wherein the one or more fabrication processes includes a manufacturing process for implanting the product wafer.

19. The method of claim 1, wherein the one or more fabrication processes includes a manufacturing process for patterning the wafer.

20. The method of claim 1, wherein (a) and (b) is performed during an inspection process for fabricating the wafer.

21. The method of claim 1, wherein (a) and (b) is performed to determine yield for fabricating the wafer.

22. The method of claim 1, wherein (a) and (b) is performed to determine yield optimization for fabricating the wafer.