Low-noise high efficiency bias generation circuits and method

• US 8,994,452 B2
• Filed: 07/17/2009
• Issued: 03/31/2015
• Est. Priority Date: 07/18/2008
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Kim, Tae Youn, Englekirk, Robert Mark, Kelly, Dylan J.
• Primary Examiner(s): NGUYEN, HIEU P
• Application Number:
  US13/054,781
• Publication Number:
  US 20110156819A1
• Time in Patent Office: 2,083 Days
• Field of Search: 330252-261
• US Class Current: 330/257
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 2200/453 Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
• CPC Class Codes: H03F 2200/456 A scaled replica of a transistor being present in an amplifier
• CPC Class Codes: H03F 2200/474 A current mirror being used as sensor
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45188 the differential amplifier contains one or more current sources in the load
• CPC Class Codes: H03F 2203/45366 the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45424 the CMCL comprising a comparator circuit
• CPC Class Codes: H03F 2203/45471 the CSC comprising one or more extra current sources
• CPC Class Codes: H03F 2203/45642 the LC, and possibly also cascaded stages following it, being (are) controlled by the common mode signal derived to control a dif amp
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03H 11/245 using field-effect transistor
• CPC Class Codes: H03K 17/145 in field-effect transistor switches

Abstract

A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A charge pump for the bias generation may include a regulating feedback loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

Claims

1. An integrated operational transconductance amplifier (“

OTA”

) having a variable-ratio current mirror differential amplifier section comprising;

a) a differential pair of FETs including a first transistor M1 having a source S1 coupled to a source S2 of a second transistor M2 and to a current source Ics, the two forming a differential input pair of FETs for the OTA, the corresponding drains of the input pair forming a pair of differential current branches;

b) an output voltage connection Vout+ coupled to one of the differential current branches;

c) a variable ratio current mirror circuit, including

i) a current sensing circuit conducting a first current through one of the differential current branches; and

ii) a current mirror reflection circuit that generates a second current substantially reflective of the first current, in the other differential current branch, the current mirror reflection circuit comprising a third transistor arranged to operate in parallel with a fourth transistor; and

d) a current mirror ratio control circuit comprising a first control FET coupled in series with the fourth transistor of the current mirror reflection circuit, the first control FET including a gate configured as a mirror ratio control node to which is applied a voltage that is continuously variable for varying a ratio between the first current conducted through the current sensing circuit and the second current conducted through the current mirror reflection circuit.

2. The OTA of claim 1, wherein the ratio is variable between 1:

K and K;

1 (K>

1), and wherein the current mirror reflection circuit is a single FET and the current sensing circuit comprises at least one FET having drain and gate coupled together.

3. The OTA of claim 1, wherein the current sensing circuit is a single FET and the current mirror reflection circuit comprises a plurality of FETs, and wherein the first control FET is coupled to sources of the plurality of current mirror reflection circuit FETs.

4. The OTA of claim 1, wherein the variable-ratio current mirror differential amplifier section is a first such section, further comprising a second variable-ratio current mirror differential amplifier section according to elements (a)-(d), the first and second amplifier sections having common inputs coupled to opposite differential inputs to produce inverting and noninverting outputs, wherein the two variable-ratio current mirrors are controlled by the same mirror ratio control node.

5. The OTA of claim 4, further comprising a circuit that couples the continuously variable voltage that is generated at an output of the OTA to the mirror ratio control node.

6. The OTA of claim 4, further comprising a separate amplification circuit that generates the voltage that is continuously variable based on a difference between the inverting and noninverting outputs.

7. The OTA of claim 1, wherein the current mirror reflection circuit comprises three FETs coupled substantially in parallel, one of the parallel FETs having a source coupled to the first control FET.

8. An integrated operational transconductance amplifier (“

OTA”

) having a variable-ratio current mirror differential amplifier section comprising;

a) a differential pair of FETs including a transistor M1 having a source S1 coupled to a source S2 of a second transistor M2 and to an approximate current source Ics, the two forming a differential input pair of FETs for the OTA, the corresponding drains of the input pair forming a pair of differential current branches;

b) an output voltage connection Vout+ coupled to one of the differential current branches; and

c) a variable ratio current mirror circuit, including

i) a current sensing circuit that is a single FET, the current sensing circuit conducting current from one of the differential current branches that generates a current control voltage reflective of the quantity of current thus conducted;

ii) a current mirror reflection circuit that generates a current substantially reflective of the current control voltage in the other differential current branch, the current mirror reflection circuit comprising a plurality of FETs having drain and gate coupled together; and

iii) a circuit, proportionally controllable by a signal applied to a mirror ratio control node that controls a control FET coupled between sources of the plurality of FETs of the mirror reflection circuit within the OTA, which aids either (A) conducting current of the current sensing circuit, or (B) producing current reflective of the current control voltage, such that

d) a ratio between current conducted by the current sensing circuit and the current mirror reflection circuit is continuously variable over a range under control of the signal applied to the mirror ratio control node.

9. An integrated operational transconductance amplifier (“

OTA”

) comprising;

a first variable-ratio current mirror differential amplifier section, comprising;

a) a differential pair of FETs including a transistor M1 having a source S1 coupled to a source S2 of a second transistor M2 and to an approximate current source Ics, the two forming a differential input pair of FETs for the OTA, the corresponding drains of the input pair forming a pair of differential current branches,

b) an output voltage connection Vout+ coupled to one of the differential current branches;

c) a variable ratio current mirror circuit, including

i) a current sensing circuit conducting current from one of the differential current branches that generates a current control voltage reflective of the quantity of current thus conducted;

ii) a current mirror reflection circuit that generates a current substantially reflective of the current control voltage in the other differential current branch; and

iii) a circuit, proportionally controllable by a signal applied to a mirror ratio control node within the OTA, which aids either (A) conducting current of the current sensing circuit, or (B) producing current reflective of the current control voltage, such that

d) a ratio between current conducted by the current sensing circuit and the current mirror reflection circuit is continuously variable over a range under control of the signal applied to the mirror ratio control node; and

a second variable-ratio current mirror differential amplifier section according to elements (a)-(d), the first and second amplifier sections having common inputs coupled to opposite differential input devices to produce two outputs inverse from each other, wherein the two variable-ratio current mirror circuits are controlled by the same mirror ratio control node.

10. The OTA of claim 9, further comprising a circuit that couples a signal substantially based on an output of the OTA to the mirror ratio control node.

11. The OTA of claim 9, further comprising a separate amplification circuit that couples a signal based on a difference between the inverting and noninverting outputs to the mirror ratio control node.

12. An integrated operational transconductance amplifier (“

OTA”

) having a variable-ratio current mirror differential amplifier section comprising;

a) a differential pair of FETs including a transistor M1 having a source S1 coupled to a source S2 of a second transistor M2 and to an approximate current source Ics, the two forming a differential input pair of FETs for the OTA, the corresponding drains of the input pair forming a pair of differential current branches;

b) an output voltage connection Vout+ coupled to one of the differential current branches; and

c) a variable ratio current mirror circuit, including

i) a current sensing circuit conducting current from one of the differential current branches that generates a current control voltage reflective of the quantity of current thus conducted;

ii) a current mirror reflection circuit that generates a current substantially reflective of the current control voltage in the other differential current branch; and

iii) a circuit comprising three FETs coupled substantially in parallel, one of the parallel FETs having a source coupled to a source of another via a first control FET, and one of the parallel FETs having a drain coupled via a second control FET to drains of the other two parallel FETs, the circuit proportionally controllable by a signal applied to a mirror ratio control node within the OTA, which aids either (A) conducting current of the current sensing circuit, or (B) producing current reflective of the current control voltage, such that

d) a ratio between current conducted by the current sensing circuit and the current mirror reflection circuit is continuously variable over a range under control of the signal applied to the mirror ratio control node.