Method of sorting a multi-bit per cell non-volatile memory and a multi-mode configuration method

• US 8,995,196 B2
• Filed: 08/15/2011
• Issued: 03/31/2015
• Est. Priority Date: 08/15/2011
• Status: Active Grant

• Current Assignee: YEESTOR Microelectronics Co., Ltd.
• Original Assignee: Skymedi Corporation
• Inventors: Huang, Han-Lung, Chou, Ming-Hung
• Primary Examiner(s): Nguyen, Tuan T
• Assistant Examiner(s): ALROBAIE, KHAMDAN N
• Application Number:
  US13/210,195
• Publication Number:
  US 20130044542A1
• Time in Patent Office: 1,324 Days
• Field of Search: 365/185.03, 365/200
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block.

Claims

1. A method of sorting a multi-bit per cell non-volatile memory, comprising:

programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has n pages associated with a word line;

if an m-th page fails the test, counting a block associated with the failed m-th page to (m−

1)-bpc blocks, where m is a positive integer from 1 through n;

wherein each said m-th page is subjected to at most one time of programming and reading, the non-volatile memory being tested in an order from the 1-st page toward the n-th page.

2. The method of claim 1, when m is equal to 1 and the 1-st page fails the test, the 0-bpc block corresponds to a bad block.

3. The method of claim 1, with respect to a given block, the 1-st pages are tested, followed by the 2-nd pages and then toward the n-th pages, and subsequently a block next to the given block is tested.

4. The method of claim 1, wherein:

(1) testing r-th pages associated with a given word line of a plurality of blocks; and

(2) repeating step (1) for r-th pages associated with another word line;

wherein steps (1) and (2) are performed at least one time for r being an integer ranged between 1 and n.

5. The method of claim 1, with respect to a given word line, test is performed in an order from the 1-st page toward the n-th page in a block, followed by performing the test in the same order in a next block.

6. The method of claim 1, with respect to two given adjacent word lines, whenever two m-th pages associated with the two given adjacent word lines have been programmed, the programmed two m-th pages are then read.

7. A multimode configuration method for a multi-bit per cell non-volatile memory, comprising:

sorting at least one n-bit-per-cell (n-bpc) non-volatile memory to obtain capacity information; and

configuring said at least one non-volatile memory according to the capacity information such that blocks of said at least one non-volatile memory are operated in distinct modes with different number of bits per cell;

wherein the sorting step comprises programming and reading to test the n-bpc non-volatile memory, which has n pages associated with a word line, each page being subjected to at most one time of programming and reading, the non-volatile memory being tested in an order from the 1-st page toward the n-th page, where m is a positive integer from 1 through n, wherein the sorting step comprises;

if the m-th page fails the test, counting a block associated with the failed m-th page to (m−

1)-bpc blocks.

8. The method of claim 7, wherein the capacity information comprises a plurality of respective numbers of p-bit-per-cell blocks, where p is a non-negative integer from 0 to n.

9. The method of claim 7, wherein a 0-bpc block corresponds to a bad block.