Method and device for sampling an input signal

• US 9,000,809 B2
• Filed: 05/30/2012
• Issued: 04/07/2015
• Est. Priority Date: 05/30/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Bogner, Peter, Faricelli, Marco
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US13/483,242
• Publication Number:
  US 20130321053A1
• Time in Patent Office: 1,042 Days
• Field of Search: 327 91- 97, 341122-125
• US Class Current: 327/94
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H03M 1/128 at random intervals, e.g. digital alias free signal processing [DASP]

Abstract

In accordance with various embodiments, a method for sampling an input signal may be provided, wherein the method may include providing a single frequency clock signal; selecting clock pulses from the single frequency clock signal in a random manner to generate a spread spectrum clock signal; and sampling the input signal using the spread spectrum clock signal. A corresponding device for sampling an input signal may be provided.

Claims

1. A method for sampling an input signal, the method comprising:

providing a single frequency clock signal;

randomly selecting at least one clock pulse from the single frequency clock signal;

delaying at least one of the randomly selected clock pulses by a random delay time to generate a spread spectrum clock signal;

sampling the input signal using the spread spectrum clock signal.

2. The method of claim 1,

wherein the single frequency clock signal is a digital signal.

3. The method of claim 1,

wherein delaying the at least one of the selected clock pulses comprises passing the at least one of the selected clock pulses through at least one delay element.

4. The method of claim 1,

wherein the input signal is a DC signal.

5. The method of claim 1,

wherein the input signal is an AC signal.

12. The method of claim 1,

wherein randomly selecting the at least one clock pulse from the single frequency clock signal comprises introducing a first jitter in the spread spectrum clock signal;

and

wherein delaying at least one of the randomly selected clock pulses by a delay time comprises introducing a second jitter different from the first jitter in the spread spectrum clock signal.

13. The method of claim 1,

wherein randomly selecting the at least one clock pulse from the single frequency clock signal comprises selecting less than all of the clock pulses from the single frequency clock signal.

6. A device for sampling an input signal, the device comprising:

a selector configured to randomly select at least one clock pulse from a single frequency clock signal;

a delay circuit configured to delay the at least one randomly selected clock pulse selected by the selector by a random delay time;

a generator configured to generate a spread spectrum clock signal from the selected and delayed clock pulses;

a sampling circuit configured to sample the input signal using the spread spectrum clock signal.

7. The device of claim 6, further comprising:

a clock signal generator configured to provide the single frequency clock signal.

8. The device of claim 7,

wherein the single frequency clock signal is a digital signal.

9. The device of claim 6,

wherein the delay circuit comprises at least one inverter.

10. The device of claim 6,

wherein the input signal is a DC signal.

11. The device of claim 6,

wherein the input signal is an AC signal.

14. The device of claim 6,

wherein randomly selecting the at least one clock pulse from the single frequency clock signal introduces a first jitter in the spread spectrum clock signal;

and

wherein delaying at least one of the randomly selected clock pulses by a delay time introduces a second jitter different from the first jitter in the spread spectrum clock signal.

15. The device of claim 6,

wherein less than all of the clock pulses of the single frequency clock signal are selected.