Power state synchronization in a multi-core processor

• US 9,009,512 B2
• Filed: 02/04/2014
• Issued: 04/14/2015
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Darius D.
• Primary Examiner(s): Patel, Nimesh G
• Application Number:
  US14/172,373
• Publication Number:
  US 20140173301A1
• Time in Patent Office: 434 Days
• Field of Search: 713/320, 713/323
• US Class Current: 713/320
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications.

Claims

1. A multi-core processor comprising:

a plurality of physical processing cores;

inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores;

wherein the inter-core state discovery microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process;

wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance;

wherein the hierarchical coordination system groups cores into a plurality of domain levels, including at least;

a primary-level domain of highest rank that includes all of the cores; and

two or more secondary-level domains of equal next rank, immediately below the highest rank, that are constituents of and nested within the primary-level domain, each secondary-level group comprising respectively exclusive subgroups of the cores;

for each multi-core domain level, a single core is designated as a master of that domain;

each multi-core domain other than the lowest-level multi-core domains defines a kinship group consisting of master cores of constituent domains of the immediately next lower rank;

each lowest-level multi-core domain defines a kinship group consisting of all of its cores;

each core belongs to at least one kinship group; and

each native instance of the synchronization logic is restricted from invoking new instances of the synchronization logic to cores not belonging to a native core kinship group.

2. The multi-core processor of claim 1, wherein:

the inter-core state discovery microcode exchanges signals with other cores through sideband communication wires that are independent of a system bus connecting the multi-core processor to a chipset; and

the inter-core state discovery microcode determines an applicable state value that is a function, at least, of a state of another core, without the assistance of any centralized non-core logic.

3. The multi-core processor of claim 1, wherein each instance of the synchronization logic is configured to invoke dependent instances of the synchronization logic on other cores of the multi-core processor in accordance with a hierarchical coordination system that structures inter-core coordinations in a hierarchical fashion.

4. The multi-core processor of claim 1, wherein the hierarchical coordination system groups cores into domains in accordance with resources shared by cores within those domains, and wherein for each domain, a single core is designated as a master of that domain for purposes of a coordinated configuration of those resources.

5. The multi-core processor of claim 1, wherein a single one of the multi-core processor'"'"'s cores is designated as a master for each multi-core domain of the hierarchical coordination system.

6. The multi-core processor of claim 1, wherein each core is configured to employ its de-centralized inter-core state discovery microcode to discover whether others of the multi-core processor'"'"'s cores are disabled.

7. The multi-core processor of claim 1, wherein each core is configured to employ its de-centralized inter-core state discovery microcode to discover how many enabled cores the multi-core processor has.

8. The multi-core processor of claim 1, wherein each core is configured to employ its de-centralized inter-core state discovery microcode to discover a hierarchical coordination system of the multi-core processor.

9. A decentralized, microcode-implemented method of discovering states of a multi-core processor comprising a plurality of physical processing cores, the method comprising:

inter-core state discovery microcode of at least two cores participating in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, exchanged by the cores;

wherein the inter-core state discovery microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process;

wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance;

wherein the hierarchical coordination system groups cores into a plurality of domain levels, including at least;

a primary-level domain of highest rank that includes all of the cores; and

two or more secondary-level domains of equal next rank, immediately below the highest rank, that are constituents of and nested within the primary-level domain, each secondary-level group comprising respectively exclusive subgroups of the cores;

for each multi-core domain level, a single core is designated as a master of that domain;

each multi-core domain other than the lowest-level multi-core domains defines a kinship group consisting of the master cores of constituent domains of the immediately next lower rank;

each lowest-level multi-core domain defines a kinship group consisting of all of its cores;

each core belongs to at least one kinship group; and

each native instance of the synchronization logic is restricted from invoking new instances of the synchronization logic to cores not belonging to a native core kinship group.

10. The method of claim 9, wherein:

the inter-core state discovery microcode exchanges signals with other cores through sideband communication wires that are independent of a system bus connecting the multi-core processor to a chipset; and

the inter-core state discovery microcode determines an applicable state value that is a function, at least, of a state of another core, without the assistance of any centralized non-core logic.

11. The method of claim 9, wherein each instance of the synchronization logic is configured to invoke dependent instances of the synchronization logic on other cores of the multi-core processor in accordance with a hierarchical coordination system that structures inter-core coordinations in a hierarchical fashion.

12. The method of claim 9, wherein the hierarchical coordination system groups cores into domains in accordance with resources shared by cores within those domains, and wherein for each domain, a single core is designated as a master of that domain for purposes of a coordinated configuration of those resources.

13. The method of claim 9, wherein a single one of the multi-core processor'"'"'s cores is designated as a master for each multi-core domain of the hierarchical coordination system.

14. The method of claim 9, wherein each core is configured to employ its de-centralized inter-core state discovery microcode to discover whether others of the multi-core processor'"'"'s cores are disabled.

15. The method of claim 9, wherein each core is configured to employ its de-centralized inter-core state discovery microcode to discover how many enabled cores the multi-core processor has.

16. The method of claim 9, wherein each core is configured to employ its de-centralized inter-core state discovery microcode to discover a hierarchical coordination system of the multi-core processor.