Processor including a cache and a scratch pad memory and memory control method thereof

• US 9,015,451 B2
• Filed: 03/14/2008
• Issued: 04/21/2015
• Est. Priority Date: 11/06/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Seoul National University R&DB Foundation (Seoul National University)
• Original Assignee: Samsung Electronics Co. Ltd., Seoul National University R&DB Foundation (Seoul National University)
• Inventors: Park, Il Hyun, Ryu, Soojung, Yoo, Dong-Hoon, Suh, Dong Kwan, Kim, Jeongwook, Jang, Choon Ki
• Primary Examiner(s): Giroux, George
• Application Number:
  US12/048,658
• Publication Number:
  US 20090119456A1
• Time in Patent Office: 2,594 Days
• Field of Search: None
• US Class Current: 712/220
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.

Claims

1. A processor comprising:

a processor core;

a cache configured to transceive data to/from the processor core via a single port, and store data accessed by the processor core; and

a Scratch Pad Memory (SPM) configured to transceive data to/from the processor core via a plurality of ports; and

a compiler configured to determine a latency value of the cache and a latency value of the SPM, and to create a schedule of instructions allocated to the cache and the SPM based solely on the determined latency value of the cache and the determined latency value of the SPM.

2. The processor of claim 1, wherein an instruction comprising at least one of a load instruction and a store instruction executed in the processor core is allocated to any one of the cache and the SPM.

3. The processor of claim 2, wherein, in response to it being undetermined while compiling which memory of the cache and the SPM the instruction executed in the processor core is to be allocated, the instruction executed in the processor core is allocated to the cache.

4. The processor of claim 2, wherein a latency value is determined based on which of the cache and the SPM the instruction executed in the processor core is allocated to, and the allocated instruction is scheduled based on the determined latency value.

5. The processor of claim 2, wherein the SPM assigns a time stamp value to an instruction allocated to the SPM, and reduces, by one, the time stamp value for each clock cycle.

6. The processor of claim 2, wherein the cache selects an instruction to be forwarded to the SPM based on an address indicated by the instruction allocated to the cache,

assigns a time stamp value to the selected instruction, and

forwards, to the SPM, the instruction to which the time stamp value is assigned.

7. The processor of claim 1, wherein a latency of the cache is less than a latency of the SPM.

8. The processor of claim 1, wherein the SPM comprises:

an input queue memory which stores, using a First In First Output (FIFO) scheme, an instruction requested by the processor core; and

an output buffer which outputs a processing result of the instruction processed by the SPM based on a latency of the processed instruction.

9. The processor of claim 8, wherein the output buffer outputs the processing result in response to a time stamp value of the processed instruction being 0.

10. The processor of claim 8, wherein, in response to a time stamp value of the instruction being predicted to be 0 while processing the instruction, the SPM transmits a stall order to the processor core.

19. The processor of claim 1, wherein the compiler is configured to:

allocate an instruction to the cache and to allocate an instruction to the SPM,

determine a latency value of the instruction allocated to the cache based on the cache,

determine a latency value of the instruction allocated to the SPM based on the SPM, and

creating a schedule of an instruction allocated to the cache and an instruction allocated to the SPM based on the determined latency values.

20. The processor of claim 1, wherein the compiler is configured to create a schedule of an instruction allocated to the cache and an instruction allocated to the SPM based on a difference between the determined latency value of the cache and the determined latency value of the SPM.

11. A memory control method of a processor including a processor core, a single port cache, and a multi-port SPM, the method comprising:

analyzing a characteristic of an instruction comprising at least one of a load instruction and a store instruction executed in the processor core;

allocating the instruction to any one of the single port cache and the multi-port SPM based on the analyzed characteristic;

determining a latency value of the single port cache and a latency value of the multi-port SPM;

creating a schedule of the instruction to be processed based solely on the determined latency value of the single port cache and the determined latency value of the multi-port SPM; and

processing the instruction based on the schedule.

12. The method of claim 11, wherein the processing comprises:

assigning a time stamp value to the instruction in response to the instruction being allocated to the multi-port SPM;

reducing, by one, the time stamp value for each clock cycle; and

outputting a processing result of the instruction in response to the time stamp value being 0.

13. The method of claim 11, wherein the processing comprises:

selecting an instruction to be forwarded to the multi-port SPM based on an address corresponding to the instruction; and

assigning a time stamp value to the selected instruction.

14. The method of claim 13, wherein the selecting comprises:

setting a start address and an end address of the single port cache; and

determining whether to forward, to the multi-port SPM, the instruction by comparing the address corresponding to the instruction with the start address and the end address.

15. The method of claim 11, wherein the multi-port SPM includes an output buffer and an input queue memory of a FIFO scheme, and

the processing comprises:

storing, in the input queue memory, the instruction according to a scheduling-determined sequence;

processing the instruction that is first stored in the input queue memory;

storing, in the output buffer, a processing result value of the processed instruction; and

outputting the processing result value stored in the output buffer in response to a time stamp value of the processed instruction being 0.

16. The method of claim 15, wherein the processing of allocated instruction further comprises:

transmitting a stall order to the processor core in response to a time stamp value of the first-stored instruction being predicted to be 0 while an operation of processing the instruction being first stored in the input queue memory is performed.

17. The method of claim 11, wherein, in response to it being undetermined while compiling which memory of the cache and the SPM the instruction executed in the processor core is to be allocated to, the allocating allocates the instruction to the cache.

18. A non-transitory computer-readable recording medium storing a program for implementing a memory control method of a processor including a processor core, a single port cache, and a multi-port SPM, the method comprising:

analyzing a characteristic of an instruction comprising at least one of a load instruction and a store instruction executed in the processor core;

allocating the instruction to any one of the single port cache and the multi-port SPM based on the analyzed characteristic;

determining a latency value of the single port cache and a latency value of the multi-port SPM;

creating a schedule of the instruction based solely on the determined latency value of the single port cache and the determined latency value of the multi-port SPM; and

processing the allocated instruction based on the schedule.