Photonic semiconductor devices in LLC assembly with controlled molding boundary and method for forming same

• US 9,018,074 B2
• Filed: 07/10/2013
• Issued: 04/28/2015
• Est. Priority Date: 10/01/2009
• Status: Active Grant

• Current Assignee: Excelitas Canada, Inc.
• Original Assignee: Excelitas Canada, Inc.
• Inventors: Zhang, Xianzhu, Deleon, Jerry, Barlow, Arthur John
• Primary Examiner(s): Hoang, Quoc
• Application Number:
  US13/938,629
• Publication Number:
  US 20140008778A1
• Time in Patent Office: 657 Days
• Field of Search: 438/456, 438/458, 257/433, 257/E21.499, 257/E21.503
• US Class Current: 438/433
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/64 : Heat extraction or cooling elements
• CPC Class Codes: H01S 5/02234 : Resin-filled housings; the housings being made of resin
• CPC Class Codes: H01S 5/02315 : Support members, e.g. bases or carriers
• CPC Class Codes: H01S 5/02326 : Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
• CPC Class Codes: H01S 5/0233 : Mounting configuration of laser chips
• CPC Class Codes: H01S 5/02345 : Wire-bonding
• CPC Class Codes: H01S 5/0235 : Method for mounting laser chips

Abstract

Embodiments of a laminate leadless carrier package are presented. The package includes an optoelectronic chip, a substrate supporting the optoelectronic chip, a plurality of conductive slotted vias, a wire bond pad disposed on the top surface of the substrate, a wire bond coupled to the optoelectronic chip and the wire bond pad and an encapsulation covering the optoelectronic chip, the wire bond, and at least a portion of the top surface of the substrate. The slotted vias provide electrical connections between the top conductive layer and the bottom conductive layer. The substrate includes a plurality of conductive and dielectric layers laminated together including a bottom conductive layer, a top conductive layer, and a dielectric layer between the top and bottom conductive layers. The encapsulation is a molding compound, and the molding compound is pulled back from at least one of the slotted vias.

Claims

1. A process for manufacturing a plurality of laminate leadless carrier packages, comprising the steps of:

preparing a substrate, wherein preparing said substrate comprises laminating a top conductive layer, a bottom conductive layer, and a dielectric layer between said top and bottom conductive layers together, and wherein said top conductive layer comprises a die attach pad, a wire bond pad, and at least two slotted vias;

applying epoxy adhesive to said die attach pad;

mounting a photonic semiconductor chip on said die attach pad;

wire-bonding said photonic semiconductor chip with said wire bond pad using a wire bond;

temporarily filling said slotted vias with temporary fillers;

molding a molding compound to form an encapsulation covering said photonic semiconductor chip, said wire bond, and at least a portion of said top surface of said substrate;

removing said temporary fillers from the slotted vias; and

dicing said substrate into individual laminate leadless carrier packages.

2. The process of claim 1, wherein said at least two slotted vias comprise a conductive via providing electrical connection between said top conductive layer and said bottom conductive layer.

3. The process of claim 1, wherein said at least two slotted vias comprise a slotted via on said top conductive layer.

4. The process of claim 3, further comprising the step of wherein said at least two slotted vias comprise a slotted via on said top conductive layer for soldering said top conductive layer to mounting pads on a printed circuit board.

5. The process of claim 4, wherein an active area of said photonic semiconductor chip is arranged perpendicular to said printed circuit board.

6. The process of claim 4, wherein an active area of said photonic semiconductor chip is arranged parallel to said printed circuit board.

7. The process of claim 1, further comprising the step of forming a boundary on said top conductive layer between said encapsulation covering and a metal contact.

8. The process of claim 7, wherein said metal contact comprises a trace on said top conductive layer configured to mechanically and/or electrically connect the photonic semiconductor devices to a mounting board in a side-looker and/or a top-looker orientation.

9. The process of claim 7, wherein said metal contact comprises at least one of said slotted vias.

10. The process of claim 7, wherein said boundary is configured to prevent contamination of said molding compound to the integrity of said metal contact.

11. The process of claim 1, wherein said wire bond pad comprises a portion of said top conductive layer.

12. The process of claim 1, wherein said molding compound is optically transparent to a band of wavelengths and filters light at particular wavelengths.

13. The process of claim 1, further comprising the step of molding said top surface of said encapsulation as a flat surface.

14. The process of claim 1, further comprising the step of molding said top surface of said encapsulation as a lens.

15. The process of claim 14, wherein said lens selected from a group consisting of a cylindrical lens, a spherical lens, a torroidal lens, an aspherical lens, and a dome-shaped lens.

16. The process of claim 1, further comprising the step of molding a footing from said encapsulation configured to stabilize said packages when mounted as side-lookers.

17. The process of claim 1, wherein said photonic semiconductor chip is selected from said group consisting of a laser, a light-emitting-diode, a PN photodiode, a phototransistor, a PIN photodiode, an avalanche photodiode, a single-photon avalanche diode, a charge coupled device, and a silicon photomultiplier.

18. The process of claim 1, wherein said substrate is selected from said group consisting of thin film ceramic substrates, thick film ceramic substrates, and printed circuit boards.

19. The process of claim 1, further comprising the step of positioning an optical filter above an active area of said photonic semiconductor chip.

20. The process of claim 1, wherein said molding further comprises encapsulating said optical filter.

21. A process for manufacturing a laminate leadless carrier package, comprising the steps of:

preparing a substrate, wherein preparing said substrate comprises laminating a top conductive layer, a bottom conductive layer, and a dielectric layer between said top and bottom conductive layers together, and wherein said top conductive layer comprises a die attach pad, a wire bond pad, and at least two slotted vias;

applying epoxy adhesive to said die attach pad;

mounting a photonic semiconductor chip on said die attach pad;

wire-bonding said photonic semiconductor chip with said wire bond pad using a wire bond;

temporarily filling said slotted vias with temporary fillers;

molding a molding compound to form an encapsulation covering said photonic semiconductor chip, said wire bond, and at least a portion of said top surface of said substrate; and

removing said temporary fillers from said slotted vias.