Processor having real-time power conservation

• US 9,021,283 B2
• Filed: 04/30/2004
• Issued: 04/28/2015
• Est. Priority Date: 10/30/1989
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Watts, LaVaughn F. Jr., Wallace, Steven J.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US10/837,106
• Publication Number:
  US 20040225906A1
• Time in Patent Office: 4,015 Days
• Field of Search: 713/300, 713320-324, 713/501, 713/600
• US Class Current: 713/322
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus having a processing unit and a monitor for monitoring activity associated with said processing unit. The monitor enables selective lowering of the frequency of clock signals, or stopping and starting of clock signals, being received by said processing unit in response to a changing level of activity associated with said processing unit.

Claims

1. A processor, comprising:

a monitor for measuring idle time within said processor, results of said measuring being used by said processor for determining which, of at least two clock signals, should be used by said processor.

2. A processor, comprising:

a monitor for measuring activity time within said processor, results of said measuring being used by said processor for determining which, of at least two clock signals, should be used by said processor.

3. A processor, comprising:

a monitor for measuring idle time and activity time within said processor, results of said measuring being used by said processor for determining which, of at least two clock signals, should be used by said processor.