Chip package and method for forming the same

  • US 9,024,437 B2
  • Filed: 06/15/2012
  • Issued: 05/05/2015
  • Est. Priority Date: 06/16/2011
  • Status: Active Grant
First Claim
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1. A chip package, comprising:

  • a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate;

    a device region formed in the substrate;

    a conducting layer disposed on the substrate and electrically connected to the device region;

    a conducting structure disposed on and covering a portion of the conducting layer;

    an insulating layer disposed between the substrate and the conducting layer;

    a protection layer disposed over the conducting layer, wherein the protection layer is configured to completely cover the conducting layer other than at the portion of the conducting layer covered by the conducting structure; and

    a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions, wherein the recess vertically exposes the carrier substrate viewed in a direction perpendicular to the substrate and the carrier substrate.

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