Chip package and method for forming the same

• US 9,024,437 B2
• Filed: 06/15/2012
• Issued: 05/05/2015
• Est. Priority Date: 06/16/2011
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: Yen, Yu-Lin, Chen, Chien-Hui, Liu, Tsang-Yu, Ho, Yen-Shih
• Primary Examiner(s): TAYLOR, EARL N
• Application Number:
  US13/524,985
• Publication Number:
  US 20120319297A1
• Time in Patent Office: 1,054 Days
• Field of Search: 257/730, 438/667
• US Class Current: 257/730
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.

Claims

1. A chip package, comprising:

a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate;

a device region formed in the substrate;

a conducting layer disposed on the substrate and electrically connected to the device region;

a conducting structure disposed on and covering a portion of the conducting layer;

an insulating layer disposed between the substrate and the conducting layer;

a protection layer disposed over the conducting layer, wherein the protection layer is configured to completely cover the conducting layer other than at the portion of the conducting layer covered by the conducting structure; and

a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions, wherein the recess vertically exposes the carrier substrate viewed in a direction perpendicular to the substrate and the carrier substrate.

2. The chip package as claimed in claim 1, wherein a sidewall of the recess inclines to at least two of the sides of the substrate.

3. The chip package as claimed in claim 1, wherein the recess has a sidewall, and the sidewall has a curved profile.

4. The chip package as claimed in claim 1, wherein a projection of at least one of the sides of the substrate on a surface of the carrier substrate overlaps with at least one side of the carrier substrate.

5. The chip package as claimed in claim 1, wherein a projection of at least one of the sides of the substrate on a surface of the carrier substrate does not overlap with any side of the carrier substrate.

6. The chip package as claimed in claim 1, wherein a projection of at least one side of the protection layer on a surface of the substrate does not overlap with the sides of the substrate.

7. The chip package as claimed in claim 1, further comprising a spacer layer disposed between the substrate and the carrier substrate.

8. The chip package as claimed in claim 7, wherein the recess exposes the spacer layer.

9. The chip package as claimed in claim 1, further comprising a hole extending from a surface of the substrate towards the carrier substrate, wherein a portion of the conducting layer is located in the hole.

10. A method for forming a chip package, comprising:

providing a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate, and wherein the substrate has a device region therein;

providing a carrier substrate;

disposing the substrate on the carrier substrate;

forming an insulating layer on the substrate;

forming a conducting layer on the insulating layer on the substrate, wherein the conducting layer is electrically connected to the device region;

forming a conducting structure disposed on and covering a portion of the conducting layer;

forming a protection layer over the conducting layer, wherein the protection layer is configured to completely cover the conducting layer other than at the portion of the conducting layer covered by the conducting layer; and

removing a portion of the substrate from at least one of the corner regions of the substrate to form a recess extending towards the carrier substrate, wherein the recess vertically exposes the carrier substrate viewed in a direction perpendicular to the substrate and the carrier substrate.

11. The method for forming a chip package as claimed in claim 10, further comprising performing a dicing process along a plurality of predetermined scribe lines of the substrate to form a plurality of chip packages separated from each other.

12. The method for forming a chip package as claimed in claim 11, wherein the dicing process comprises cutting the substrate and then cutting the carrier substrate or cutting the carrier substrate and then cutting the substrate.

13. The method for forming a chip package as claimed in claim 10, wherein the step of forming the recess comprises removing the portion of the substrate by using a dicing process, an etching process, or combinations thereof.

14. The method for forming a chip package as claimed in claim 10, further comprising removing a portion of the substrate such that a projection of at least one of the sides of the substrate on a surface of the carrier substrate does not overlap with any side of the carrier substrate.

15. The method for forming a chip package as claimed in claim 10, further comprising:

removing a portion of the substrate from a surface of the substrate to form a hole extending towards the carrier substrate; and

after the hole is formed, forming the insulating layer on the substrate and forming the conducting layer on the insulating layer, wherein a portion of the insulating layer and a portion of the conducting layer are located in the hole.

16. The method for forming a chip package as claimed in claim 15, wherein the hole and the recess are simultaneously formed.

17. The method for forming a chip package as claimed in claim 10, wherein the step of forming the recess comprises:

performing a dicing process along a plurality of predetermined scribe lines of the substrate by using a first blade to remove a portion of the substrate; and

performing a second dicing process along the predetermined scribe lines of the substrate by using a second blade to cut through the substrate and the carrier substrate, wherein a width of the first blade is larger than that of the second blade.

18. The method for forming a chip package as claimed in claim 10, wherein a projection of at least one side of the protection layer on the surface of the substrate does not overlap with the sides of the substrate.

19. A chip package, comprising:

a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate;

a device region formed in the substrate;

a conducting layer disposed on the substrate and electrically connected to the device region;

an insulating layer disposed between the substrate and the conducting layer; and

a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions to form a truncated corner, wherein the recess is formed only in the at least one of the corner regions, and the recess vertically exposes the carrier substrate viewed in a direction perpendicular to the substrate and the carrier substrate.