Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support

• US 9,029,193 B2
• Filed: 05/06/2010
• Issued: 05/12/2015
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Marimuthu, Pandi Chelvam, Suthiwongsunthorn, Nathapong, Heng, Kock Liang
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US12/775,170
• Publication Number:
  US 20100221873A1
• Time in Patent Office: 1,832 Days
• Field of Search: None
• US Class Current: 438/106
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

Claims

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first interconnect structure, including a plurality of conductive pillars, over a first surface of the substrate;

disposing a semiconductor die over the first interconnect structure with bumps electrically connected to the conductive pillars;

depositing an encapsulant over the semiconductor die and first interconnect structure;

forming a via through a second surface of the substrate, opposite the first surface of the substrate, to the first interconnect structure; and

forming a second interconnect structure in the via.

2. The method of claim 1, wherein forming the second interconnect structure includes:

applying an insulating layer over a sidewall of the via; and

forming a conductive layer over the insulating layer in the via.

3. The method of claim 1, wherein the via includes a tapered sidewall.

4. The method of claim 1, wherein forming the first interconnect structure includes:

forming a first conductive layer over the first surface of the substrate;

forming a first insulating layer over the first conductive layer and substrate;

forming a second conductive layer over the first insulating layer and first conductive layer;

forming a second insulating layer over the second conductive layer and first insulating layer;

forming a conductive pillar over the second conductive layer;

forming a third insulating layer around the conductive pillar; and

forming a third conductive layer over the conductive pillar and electrically connecting the third conductive layer to the semiconductor die.

5. The method of claim 1, wherein forming the second interconnect structure further includes forming a bump in the via over the first interconnect structure.

6. The method of claim 1, further including mounting the semiconductor device to a printed circuit board through the second interconnect structure.

7. The method of claim 1, wherein forming the second interconnect structure includes:

forming an insulating layer over the first interconnect structure; and

forming a bump over the first interconnect structure.

8. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first interconnect structure, including a plurality of conductive pillars, over a first surface of the substrate;

disposing a semiconductor die over the first interconnect structure with bumps electrically connected to the conductive pillars;

depositing an encapsulant over the semiconductor die and first interconnect structure;

forming a via through a second surface of the substrate, opposite the first surface of the substrate, to the first interconnect structure; and

forming a first conductive layer in the via.

9. The method of claim 8, further including forming a second interconnect structure over the first conductive layer.

10. The method of claim 9, wherein forming the second interconnect structure includes forming a bump in the via over the first conductive layer.

11. The method of claim 8, wherein the via includes a tapered sidewall.

12. The method of claim 8, further including removing a portion of the substrate to reduce a thickness of the substrate.

13. The method of claim 8, wherein forming the first interconnect structure includes:

forming a second conductive layer over the first surface of the substrate;

forming a first insulating layer over the second conductive layer and substrate;

forming a third conductive layer over the first insulating layer and second conductive layer;

forming a second insulating layer over the third conductive layer and first insulating layer;

forming a conductive pillar over the third conductive layer;

forming a third insulating layer around the conductive pillar; and

forming a fourth conductive layer over the conductive pillar and electrically connecting the third conductive layer to the semiconductor die.

14. The method of claim 8, further including forming an insulating layer over a sidewall of the via.

15. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first interconnect structure, including a plurality of conductive pillars, over a first surface of the substrate;

disposing a semiconductor die over the first interconnect structure;

depositing an encapsulant over the semiconductor die and first interconnect structure;

forming a via through a second surface of the substrate, opposite the first surface of the substrate, to the first interconnect structure; and

forming a first conductive layer over a sidewall of the via.

16. The method of claim 15, further including forming an insulating layer over the sidewall of the via.

17. The method of claim 15, further including forming a second interconnect structure over the first conductive layer.

18. The method of claim 17, wherein forming the second interconnect structure includes forming a bump in the via over the first conductive layer.

19. The method of claim 15, further including removing a portion of the substrate to reduce a thickness of the substrate.

20. The method of claim 15, wherein forming the first interconnect structure includes:

forming a second conductive layer over the first surface of the substrate;

forming a first insulating layer over the second conductive layer and substrate;

forming a third conductive layer over the first insulating layer and second conductive layer;

forming a second insulating layer over the third conductive layer and first insulating layer;

forming a conductive pillar over the third conductive layer;

forming a third insulating layer around the conductive pillar; and

forming a fourth conductive layer over the conductive pillar and electrically connecting the fourth conductive layer to the semiconductor die.

21. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first interconnect structure over a first surface of the substrate;

disposing a semiconductor die over the first interconnect structure;

depositing an encapsulant over the semiconductor die and extending to the substrate;

forming an opening in the substrate extending to the first interconnect structure; and

forming a second interconnect structure over the substrate and into the opening in the substrate to contact the first interconnect structure.

22. The method of claim 21, wherein forming the first interconnect structure includes:

forming a first conductive layer over the first surface of the substrate;

forming a first insulating layer over the first conductive layer and substrate;

forming a second conductive layer over the first insulating layer and first conductive layer;

forming a second insulating layer over the second conductive layer and first insulating layer;

forming a conductive pillar over the second conductive layer;

forming a third insulating layer around the conductive pillar; and

forming a third conductive layer over the conductive pillar and electrically connecting the third conductive layer to the semiconductor die.

23. The method of claim 21, wherein forming the second interconnect structure includes:

forming an insulating layer over the first interconnect structure; and

forming a bump over the first interconnect structure.