Clock recovery circuit

• US 9,036,764 B1
• Filed: 10/09/2013
• Issued: 05/19/2015
• Est. Priority Date: 12/07/2012
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Hossain, Masum, Zerbe, Jared L., Park, Myeong-Jae
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US14/050,202
• Time in Patent Office: 587 Days
• Field of Search: 375/355, 375/371, 375/373, 375/374, 375/376, 327/155, 327/156, 327/157
• US Class Current: 375/376
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 2025/03445 Time domain
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator'"'"'s (VFO'"'"'s) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

Claims

1. A clock recovery circuit, comprising:

a phase-locked loop having

a first phase comparator operable to compare a timing reference signal with feedback of a recovered clock signal,

circuitry operable to low pass filter an output of the first phase comparator,

a variable frequency oscillator controlled responsive to an output of the circuitry to generate the recovered clock signal; and

at least one second phase comparator operable to generate (i) a binary signal dependent on comparison between an input data signal and the recovered clock signal and (ii) a signal that varies linearly dependent on comparison between the input data signal and the recovered clock signal;

wherein the phase-locked loop is operable to receive the binary signal and the signal that varies linearly, to apply the binary signal to adjust the feedback of the recovered clock signal, and to apply the linearly-varying signal to adjust the output of the circuitry so as to adjust generation of the recovered clock signal by the variable frequency oscillator.

2. The clock recovery circuit of claim 1, embodied as an integrated circuit, wherein the clock recovery circuit further comprises a conductive element operable to connect electrically to a link external to the integrated circuit to receive the input data signal.

3. The clock recovery circuit of claim 2, wherein the clock recovery circuit further comprises a conductive element operable to connect electrically to a link external to the integrated circuit to receive the timing reference signal.

4. The clock recovery circuit of claim 1, wherein the at least one second phase comparator is embodied in common as a hybrid phase detector, the hybrid phase detector operable to generate both of the binary signal and the signal that varies linearly.

5. The clock recovery circuit of claim 1, wherein the at least one second phase comparator is operable to generate the signal that varies linearly as a continuous-time signal having a magnitude that varies linearly dependent on difference between the input data signal and the recovered clock signal.

6. The clock recovery circuit of claim 1, wherein the at least one second phase comparator comprises at least one of a sample-and-hold circuit and an integration circuit, the at least one of the sample-and-hold circuit and the integration circuit operable to generate the signal that varies linearly.

7. The clock recovery circuit of claim 1, wherein the at least one second phase comparator comprises a bang-bang phase detector operable to generate the binary signal dependent on comparison between an input data signal and the recovered clock signal.

8. The clock recovery circuit of claim 1, wherein the phase-locked loop further comprises a second order response filter operable to receive the binary signal, to accumulate first order and second order phase error, and to output a phase correction signal responsive to the accumulated first order and second order phase error.

9. The clock recovery circuit of claim 1, wherein the phase-locked loop further comprises a phase interpolator coupled to the variable frequency oscillator to receive phases of the recovered clock signal and operable to generate the feedback of the recovered clock signal from the phases dependent on the binary signal.

10. The clock recovery circuit of claim 1, wherein the circuitry is further operable to generate a control signal for the variable frequency oscillator to have a magnitude, and where the phase-locked loop further comprises circuitry operable to modify the magnitude responsive to the signal that varies linearly.

11. The clock recovery circuit of claim 10, wherein the circuitry operable to generate the control signal generates the control signal to have a voltage magnitude associated with an output frequency of the variable frequency oscillator, and where the at least one second phase comparator is operable to generate the signal that varies linearly in voltage magnitude dependent on difference between the input data signal and the recovered clock signal.

12. The clock recovery circuit of claim 11, wherein the phase-lock loop comprises circuitry operable to sum the signal that varies linearly with the control signal to generate a signal having a combined magnitude, and where the variable frequency oscillator is controlled responsive to the combined magnitude.

13. An improvement in a clock recovery circuit having a phase-locked loop, circuitry operable to determine whether transitions of a recovered clock are early or late relative to an incoming data signal and to responsively generate a binary phase-error signal, a variable frequency oscillator operable to generate the recovered clock, and circuitry operable to generate in response to the binary phase-error signal a control signal having a magnitude, the frequency of the variable frequency oscillator dependent on the magnitude of the control signal, the improvement comprising:

comparing the incoming data signal with the recovered clock to also generate a signal that varies linearly dependent on difference between the incoming data signal and the recovered clock; and

modifying the magnitude in dependence on the signal that varies linearly.

14. The improvement of claim 13, wherein the improvement is embodied in an integrated circuit and is further characterized by:

a conductive element of the integrated circuit operable to connect electrically to a link external to the integrated circuit to receive the incoming data signal;

a conductive element of the integrated circuit operable to connect electrically to a link external to the integrated circuit to receive a timing reference signal; and

a phase comparator operable to receive the timing reference signal and to compare the timing reference signal with a feedback clock phase selected in dependence on the binary phase-error signal, the control signal dependent on output of the phase comparator.

15. The improvement of claim 13, further characterized by use of a hybrid phase detector circuit operable to generate both of the binary phase-error signal and the signal that varies linearly.

16. The improvement of claim 13, wherein the signal that varies linearly is a continuous-time signal having a magnitude that varies linearly dependent on difference between the incoming data signal and a recovered clock signal.

17. The improvement of claim 13, further comprising an integration circuit operable to generate the signal that varies linearly.

18. The improvement of claim 13, further comprising a sample-and-hold circuit operable to generate the signal that varies linearly.

19. The improvement of claim 13, wherein:

the improvement further comprises a phase interpolator coupled to the variable frequency oscillator to receive phases of a recovered clock signal and operable to output a feedback signal having a phase selected in response to the binary signal; and

the circuitry operable to generate further comprises a phase comparator operable to compare edges of the feedback signal with edges of a timing reference signal, to responsively generate the control signal.

20. The improvement of claim 13, wherein the circuitry operable to generate the control signal generates the control signal to have a voltage magnitude associated with an output frequency of the variable frequency oscillator, and wherein the circuitry operable to generate is operable to generate the control signal to vary linearly in voltage magnitude dependent on difference between the input data signal and a recovered clock signal.

21. The improvement of claim 20, further comprising circuitry operable to sum the signal that varies linearly with the control signal to generate a signal having a combined magnitude, and where the variable frequency oscillator is controlled responsive to the combined magnitude.

22. A clock recovery circuit operable to receive an input data signal, the clock recovery circuit comprising:

a phase comparator operable to compare a recovered clock signal with the input data signal and to responsively generate a binary output representing phase error;

circuitry operable to accumulate the binary output and to responsively generate an accumulated output having a magnitude responsive to accumulated error;

a phase comparator operable to compare the recovered clock signal with the input data signal and to responsively generate an output that linearly varies dependent on amount of error; and

a variable frequency oscillator controller operable to vary frequency of the recovered clock responsive to the magnitude;

wherein the magnitude is adjusted responsive to the output that varies linearly dependent on the amount of error.

23. The clock recovery circuit of claim 22, wherein:

the magnitude is a voltage magnitude;

the output that varies linearly dependent on the amount of error is generated to have a voltage level that varies linearly dependent on the amount of error; and

the clock recovery circuit adjusts the magnitude by combining the control signal with the output that varies linearly dependent on the amount of error.