Methods and systems for mapping a peripheral function onto a legacy memory interface
First Claim
1. A dual-inline memory module (DIMM) comprising:
- a module interface configured to receive module data into the DIMM using parallel data channels;
a non-volatile flash memory bank; and
one or more integrated circuits, including a processor or controller, configured to receive the module data using the parallel data channels before the module data is provided to either the non-volatile flash memory bank or a volatile random access memory (VRAM) bank and to enable the module data to be written to the VRAM bank, read from the VRAM bank, and written to the non-volatile flash memory bank,wherein the one or more integrated circuits are configured to translate between a first addressing scheme employed by the VRAM bank and a second addressing scheme employed by the non-volatile flash memory bank,wherein the one or more integrated circuits are configured to enable;
the module data to be written to the VRAM bank employing the first addressing scheme,the module data written to the VRAM bank employing the first addressing scheme to be read,the module data read from the VRAM bank to be translated from the first addressing scheme employed by the VRAM bank to the second addressing scheme employed by the non-volatile flash memory bank, andthe module data translated to the second addressing scheme employed by the non-volatile flash memory bank to be written to the non-volatile flash memory bank employing the second addressing scheme.
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Accused Products
Abstract
A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
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Citations
17 Claims
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1. A dual-inline memory module (DIMM) comprising:
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a module interface configured to receive module data into the DIMM using parallel data channels; a non-volatile flash memory bank; and one or more integrated circuits, including a processor or controller, configured to receive the module data using the parallel data channels before the module data is provided to either the non-volatile flash memory bank or a volatile random access memory (VRAM) bank and to enable the module data to be written to the VRAM bank, read from the VRAM bank, and written to the non-volatile flash memory bank, wherein the one or more integrated circuits are configured to translate between a first addressing scheme employed by the VRAM bank and a second addressing scheme employed by the non-volatile flash memory bank, wherein the one or more integrated circuits are configured to enable; the module data to be written to the VRAM bank employing the first addressing scheme, the module data written to the VRAM bank employing the first addressing scheme to be read, the module data read from the VRAM bank to be translated from the first addressing scheme employed by the VRAM bank to the second addressing scheme employed by the non-volatile flash memory bank, and the module data translated to the second addressing scheme employed by the non-volatile flash memory bank to be written to the non-volatile flash memory bank employing the second addressing scheme. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A dual-inline memory module (DIMM) comprising:
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a module interface configured to receive module data into the DIMM using parallel data channels; a non-volatile flash memory bank; and means for one or more integrated circuits, including a processor or controller, configured to receive the module data using the parallel data channels before the module data is provided to either the non-volatile flash memory bank or a volatile random access memory (VRAM) bank and to enable the module data to be written to the VRAM bank, read from the VRAM bank, and written to the non-volatile flash memory bank, wherein the one or more integrated circuits are configured to translate between a first addressing scheme employed by the VRAM bank and a second addressing scheme employed by the non-volatile flash memory bank, wherein the one or more integrated circuits are configured to enable; the module data to be written to the VRAM bank employing the first addressing scheme, the module data written to the VRAM bank employing the first addressing scheme to be read, the module data read from the VRAM bank to be translated from the first addressing scheme employed by the VRAM bank to the second addressing scheme employed by the non-volatile flash memory bank, and the module data translated to the second addressing scheme employed by the non-volatile flash memory bank to be written to the non-volatile flash memory bank employing the second addressing scheme. - View Dependent Claims (12, 13)
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14. A system comprising:
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a central processing unit (CPU) with a memory controller configured to direct delivery of module data from the CPU to module memory using parallel data channels; and a dual-inline memory module (DIMM) configured to receive the module data from the CPU, including; a module interface configured to receive the module data into the DIMM using parallel data channels, a non-volatile flash memory bank, and one or more integrated circuits, including a processor or controller, configured to receive the module data using the parallel data channels before the module data is provided to either the non-volatile flash memory bank or a volatile random access memory (VRAM) bank and to enable the module data to be written to the VRAM bank, read from the VRAM bank, and written to the non-volatile flash memory bank, wherein the one or more integrated circuits are configured to translate between a first addressing scheme employed by the VRAM bank and a second addressing scheme employed by the non-volatile flash memory bank, wherein the one or more integrated circuits are configured to enable; the module data to be written to the VRAM bank employing the first addressing scheme, the module data written to the VRAM bank employing the first addressing scheme to be read, the module data read from the VRAM bank to be translated from the first addressing scheme employed by the VRAM bank to the second addressing scheme employed by the non-volatile flash memory bank, and the module data translated to the second addressing scheme employed by the non-volatile flash memory bank to be written to the non-volatile flash memory bank employing the second addressing scheme. - View Dependent Claims (15, 16, 17)
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Specification