High voltage monitoring successive approximation analog to digital converter

• US 9,044,614 B2
• Filed: 03/17/2014
• Issued: 06/02/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Alfred E. Mann Foundation For Scientific Research
• Original Assignee: Alfred E. Mann Foundation For Scientific Research
• Inventors: Lee, Edward K. F.
• Primary Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US14/217,329
• Publication Number:
  US 20140277269A1
• Time in Patent Office: 442 Days
• Field of Search: 341/172, 341/155, 341/156, 341/118, 341/120, 600/561, 607/46, 607/2, 607/59
• US Class Current: 1/1
• CPC Class Codes: A61N 1/36071 Pain
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/37235 Aspects of the external programmer
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/129 Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling H03M1/18 takes precedence; Out-of-range indication
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/685 the quantisation value generators of both converters being arranged in a common two-dimensional array
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A successive approximation ADC made of a low voltage configurable differential amplifier and low voltage logic circuits which can convert a high voltage analog input to a digital equivalent. The differential amplifier can be configured as either an op amp or a comparator depending upon the mode of operation. An input capacitor C1 is switchably coupled to an electrode selected for voltage sampling. A switched capacitor array C2 is coupled across the differential amplifier input and output. A SAR coupled to the switched capacitor array provides a digital output corresponding to the sampled analog voltage. During a sampling interval and a charge transfer interval, the differential amplifier is configured as an op amp. During the transfer interval, the voltage on the input capacitor multiplied by the ratio C1/C2 is transferred to the switched capacitor array. During an analog to digital conversion interval, the ADC converts the analog voltage to an equivalent digital output.

Claims

1. An analog to digital converter (ADC) comprising:

a switched capacitor array, wherein the capacitor array has a total capacitance value of C2;

a differential amplifier selectably configurable as either an operational amplifier or a comparator, said differential amplifier having first and second inputs and an output, wherein the first input is coupled to a reference voltage and wherein the switched capacitor array is coupled across the second input and the output of the differential amplifier;

an input capacitor switchably coupled between the differential amplifier second input and an analog voltage source adapted to provide an analog voltage signal to be converted to a digital output signal, said input capacitor having a capacitance value of C1;

a successive approximation register coupled to the switched capacitor array and the differential amplifier output and configured to provide the digital output signal; and

a logic signal generator configured to provide timing control logic signals arranged to;

(a) charge the input capacitor to the value of the analog voltage signal and configure the differential amplifier as an operational amplifier during a sampling interval such that a virtual ground is established at the differential amplifier second input for facilitating charge transfer from the input capacitor to the switched capacitor array;

(b) transfer the analog voltage signal on the input capacitor multiplied by the ratio C1/C2 to the capacitor array during a transfer interval; and

(c) configure the differential amplifier as a comparator for comparing the reference voltage to the voltage on the switched capacitor array, wherein the capacitors in the switched capacitor array are switched for converting the voltage on the capacitor array to digital output bits for storage in the successive approximation register according to the comparator output in a successive approximation protocol during an analog to digital conversion interval to thereby provide the digital output signal.

2. The ADC of claim 1 wherein the timing control logic comprises a first logic signal for controlling the sampling interval, a second logic signal for controlling the transfer interval and a third logic signal for controlling the analog to digital conversion interval, wherein said logic signals have logic states “

1” and

“

0”

, wherein switches controlled by respective logic signals are closed when the respective controlling logic signal is at a logic “

1” and

open when the respective controlling logic signal is at a “

0”

.

3. The ADC of claim 2 further comprising a first switch controlled by the first logic signal and configured to switchably couple the analog voltage signal to the input capacitor.

4. The ADC of claim 2 further comprising a second switch controlled switch configured by the second logic signal and configured to switchably couple said input capacitor to ground.

5. The ADC of claim 2 further comprising a third switch controlled by the third logic signal and configured to switchably couple, through said input capacitor, the analog voltage signal to the differential amplifier second input.

6. The ADC of claim 2 further comprising a fourth switch controlled by the first logic signal and configured to couple the differential amplifier output to the differential amplifier second input so as to configure the differential amplifier as an op amp when the first logic signal is at logic “

1”

.

7. The ADC of claim 2 wherein when the first logic signal is at logic “

0” and

the second logic signal is at logic “

1”

the capacitors in the switched capacitor array are configured to be coupled across the differential amplifier output and second input.

8. The ADC of claim 2 wherein during a conversion phase the timing control logic causes the timing of the third logic signal to be at logic “

0”

wherein the differential amplifier is configured as a comparator and wherein the voltage on the capacitor array is converted to digital output bits.

9. The ADC of claim 2 wherein said third logic signal is coupled to the differential amplifier in a manner so as to configure the differential amplifier as an op amp when the third logic signal is at logic “

1” and

to configure the differential amplifier as a comparator when the third logic signal is at logic “

0”

.

10. The ADC of claim 1 wherein during the transfer interval, the analog voltage signal on the input capacitor is:

(a) attenuated by the ratio of C1/C2 when the value of C2 is greater than the value of C1; and

(b) amplified by the ratio of C1/C2 when the value of C2 is less than the value of C1. amplifier as a comparator when the third logic signal is at logic “

0”

.

11. A method of converting an analog signal to a digital equivalent signal utilizing an analog to digital converter, said converter comprising:

a differential amplifier configurable as either an op amp or a comparator, said differential amplifier having first and second inputs and an output, wherein a reference voltage is coupled to the first input;

a capacitor array coupled across the second input and the output, said capacitor array having a total capacitance value of C2;

an input capacitor switchably coupled between a source of analog signals and the second input, said input capacitor having a capacitance value of C1;

a successive approximation register coupled to the switched capacitor array and the differential amplifier output; and

a logic signal generator configured to provide timing control logic signals to;

define a sampling interval, define a transfer interval and define an analog to digital conversion interval respectively, the method comprising;

sampling the analog signal onto the input capacitor during the sampling interval wherein the differential amplifier is configured as an op amp;

transferring the sampled signal on the input capacitor multiplied by the ratio C1/C2 during the transfer interval to the switched capacitor array, wherein the differential amplifier is configured as an op amp; and

configuring the differential amplifier as a comparator and converting the voltage on the capacitor array to digital output bits for storage in the successive approximation register according to the comparator output in a successive approximation protocol during an analog to digital conversion interval to thereby provide the digital equivalent signal.

12. A peripherally-implantable neurostimulation system comprising:

a plurality of leads, wherein each of the plurality of leads comprises at least one electrode;

an analog-to-digital converter comprising a successive approximation analog-to-digital converter and an integral switched capacitor amplifier, wherein the successive approximation analog-to-digital converter and the integral switched capacitor amplifier share a common differential amplifier; and

a pulse generator configured to generate one or several electrical pulses, wherein the pulse generator is connected to the leads such that the electrical pulses are transmitted to the at least one electrode.

13. The peripherally-implantable neurostimulation system of claim 12, further comprising a successive approximation register.

14. The peripherally-implantable neurostimulation system of claim 13, wherein the successive approximation register comprises a logic signal generator.

15. The peripherally-implantable neurostimulation system of claim 14, wherein the logic signal generator is configured to generate a first signal directing the differential amplifier to operate as an opamp during a first period, and a second signal directing the differential amplifier to operate as a comparator during a second period.

16. The peripherally-implantable neurostimulation system of claim 15, further comprising an input capacitor between the leads and the analog-to-digital converter, wherein the input capacitor is charged during the first period.

17. The peripherally-implantable neurostimulation system of claim 16, wherein the input capacitor is discharged during the first period and subsequent to the charging of the input capacitor, and wherein the charge is transferred to a switched capacitor array.

18. An implantable electrical stimulation system comprising:

a pulse generator configured to generate one or several electrical pulses;

an electrode array configured to output the one or several electrical pulses;

an analog-to-digital converter configured to convert an analog signal associated with at least one of the electrodes of the electrode array to a digital signal, the analog-to-digital converter including a reconfigurable differential amplifier; and

a controller configured to reconfigure the differential amplifier between an operational amplifier mode and a comparator mode.

19. The implantable electrical stimulation system of claim 18, wherein the analog-to-digital converter comprises a successive approximation analog-to-digital converter and a switched capacitor amplifier that share a common differential amplifier.

20. The implantable electrical stimulation system of claim 19, further comprising a successive approximation register.

21. The implantable electrical stimulation system of claim 18, wherein the controller is configured to generate a first signal directing the reconfigurable differential amplifier to operate as an opamp during a first period, and a second signal directing the differential amplifier to operate as a comparator during a second period.

22. The implantable electrical stimulation system of claim 21, further comprising an input capacitor connecting the leads and the analog-to-digital converter, wherein the input capacitor is charged during the first period.

23. The implantable electrical stimulation system of claim 22, wherein the input capacitor is discharged during the first period and subsequent to the charging of the input capacitor, and wherein the charge is transferred to a switched capacitor array.

24. A method of treating neuropathic pain, comprising:

delivering at least one electrical pulse to a body tissue proximate or at a nerve by an implanted pulse generator and at least one electrode;

sensing an analog attribute of the at least one electrical pulse using a differential amplifier configured in an operational amplifier mode; and

converting the sensed analog attribute to a digital signal using the differential amplifier configured in a comparator mode.

25. The method of claim 24, wherein delivering the at least one electrical pulse comprises delivering the at least one electrical pulse to a peripheral body tissue proximate to or at a peripheral nerve.

26. The method of claim 24, wherein the electrical pulse has a first property.

27. The method of claim 26, wherein the digital signal indicates the presence or absence of a short or open circuit.

28. The method of claim 27, further comprising delivering a second electrical pulse having a second property, wherein the second property of the second electrical pulse is based on the first property of the electrical pulse and the digital signal.

29. The method of claim 26, wherein the digital signal indicates the voltages of the at least one electrode.

30. The method of claim 29, further comprising delivering a second electrical pulse having a second property, wherein the second property of the second electrical pulse is based on the first property of the electrical pulse and the digital signal.