Dual-gate trench IGBT with buried floating P-type shield

• US 9,048,282 B2
• Filed: 03/14/2013
• Issued: 06/02/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hu, Jun, Bobde, Madhur, Yilmaz, Hamza
• Primary Examiner(s): Rodriguez, Armando
• Assistant Examiner(s): Alam, Mohammed R
• Application Number:
  US13/831,066
• Publication Number:
  US 20140264433A1
• Time in Patent Office: 810 Days
• Field of Search: 257/139, 257E29027-E29028, 257E29066-E29067, 257E29194-E29202
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

Claims

1. An insulated gate bipolar transistor (IGBT) device supported in a semiconductor substrate wherein:

the semiconductor substrate comprising an epitaxial layer of a first conductivity type supported on a bottom layer of a second conductivity type electrically contacting a collector electrode disposed on a bottom surface of the semiconductor substrate;

the IGBT device further comprises a body region of the second conductivity type disposed near a top surface of the semiconductor substrate encompassing a source region of the first conductivity type below a top surface of the semiconductor substrate;

the epitaxial layer further includes an upper heavily doped layer having a higher dopant concentration of the first conductivity type below the body region;

the IGBT device further comprises a trench gate and a planar gate disposed on the top surface of the semiconductor substrate wherein the trench gate extends downwardly below and substantially from a midpoint of the planar gate; and

at least a second trench filled with a gate material disposed at substantially a periphery portion of the IGBT device at a distance away from the trench gate and the planar gate and is electrically connected to a source electrode.

2. The IGBT device of claim 1 wherein:

the trench gate is electrically connected to a gate electrode.

3. The IGBT device of claim 1 wherein:

the planar gate is electrically connected to a gate electrode.

4. The IGBT device of claim 1 wherein:

the trench gate and the second trench filled with the gate material are padded with a gate insulation layer and filled with the gate material comprises a polysilicon layer.

5. The IGBT device of claim 1 wherein:

the trench gate and the second trench filled with the gate material are padded with a gate insulation layer having a thickness of approximately 5000 Angstroms and the trench gate and the second trench filled with the gate material are filled with a polysilicon layer.

6. The IGBT device of claim 1 wherein:

the trench gate and the second trench filled with the gate material extend vertically to approximately a bottom surface of the upper heavily dope region above the epitaxial layer.

7. The IGBT device of claim 1 wherein:

the upper heavily doped region comprising a heavily N-doped region above the epitaxial layer of an N-type conductivity disposed above the substrate of a P-type conductivity type.

8. The IGBT device of claim 1 further comprising:

a floating buried ring comprising a dopant region of the second conductivity type disposed below a trench bottom surface of the second trench filled with the gate material.

9. The IGBT device of claim 1 further comprising:

a floating buried ring comprising a dopant region of the second conductivity type disposed below a trench bottom surface of the second trench filled with the gate material.

10. The IGBT device of claim 1 wherein:

the upper heavily doped layer functioning together with the epitaxial layer as a base region of the IGBT, and the body region functioning as a channel region from the source region to the base region of the IGBT.

11. The IGBT device of claim 1 wherein:

the planar gate extends substantially perpendicularly to the trench gate.

12. The IGBT device of claim 1 further comprising:

a floating buried ring of the second conductivity type disposed below a trench bottom surface of the second trench filled with the gate material; and

the floating buried ring comprising buried dopant islands of the second conductivity type disposed at selected locations along the trench bottom surface of the second trench filled with the gate material and electrically connected to a source electrode.