Nitride semiconductor wafer, nitride semiconductor device, and method for manufacturing nitride semiconductor wafer

• US 9,053,931 B2
• Filed: 09/25/2012
• Issued: 06/09/2015
• Est. Priority Date: 09/05/2012
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshida, Hisashi, Hikosaka, Toshiki, Harada, Yoshiyuki, Sugiyama, Naoharu, Nunoue, Shinya
• Primary Examiner(s): Campbell, Shaun
• Assistant Examiner(s): Vuong, Thai T
• Application Number:
  US13/626,265
• Publication Number:
  US 20140061693A1
• Time in Patent Office: 987 Days
• Field of Search: 257/13, 257/22, 257/76, 257/194, 257/615, 438/37
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD

Abstract

According to one embodiment, a nitride semiconductor wafer includes: a silicon substrate; a buffer section provided on the silicon substrate; and a functional layer provided on the buffer section and contains nitride semiconductor. The buffer section includes first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor. An i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer. An (i+1)-th buffer layer provided on the i-th buffer layer has a lattice length W(i+1) in the first direction. In the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfy relation of (W(i+1)−Wi)/Wi≦0.008.

Claims

1. A nitride semiconductor wafer comprising:

a silicon substrate;

a buffer section provided on the silicon substrate; and

a functional layer provided on the buffer section and comprising a nitride semiconductor,

wherein;

the buffer section comprises first to n-th buffer layers comprising a nitride semiconductor, n being an integer of 4 or more;

an i-th buffer layer, i being an integer of 1 or more and less than n, of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer;

an (i+1)-th buffer layer in direct contact with the i-th buffer layer has a lattice length W(i+1) in the first direction; and

in the first to n-th buffer layers, the i-th buffer layer and the (i+1)-th buffer layer satisfy a relation of 0.003≦

(W(i+1)-Wi)/Wi≦

0.008.

2. The wafer according to claim 1, wherein

the major surface is a c-plane, and

the first direction is an a-axis direction.

3. The wafer according to claim 1, wherein

the first buffer layer comprises Al_x1Ga₁₋

x1N (0<

x1≦

1),

the n-th buffer layer comprises Al_xnGa<sub>1−

xn</sub>N (0≦

xn<

1), and

the i-th buffer layer between the first buffer layer and the n-th buffer layer comprises Al_xiGa<sub>1−

xi</sub>N (0<

xi1<

1).

4. The wafer according to claim 3, wherein the Al composition ratio of the (i+1)-th buffer layer is lower than the Al composition ratio of the i-th buffer layer.

5. The wafer according to claim 1, wherein lattice mismatch in the first direction between the first buffer layer and the n-th buffer layer is from 1.9% to 2.5%.

6. The wafer according to claim 1, wherein n is 9 or less.

7. The wafer according to claim 1, wherein the (i+1)-th buffer layer has a relaxation of 0.65 or less.

8. The wafer according to claim 1, wherein the functional layer comprises:

a first semiconductor layer of a first conductivity type provided on the buffer section;

a light emitting layer provided on the first semiconductor layer; and

a second semiconductor layer of a second conductivity type provided on the light emitting layer.

9. The wafer according to claim 8, wherein

the light emitting layer comprises a plurality of barrier layers and a well layer provided between the plurality of barrier layers, and

a bandgap energy of the barrier layer is larger than a bandgap energy of the well layer.

10. The wafer according to claim 9, wherein

the barrier layers comprise a nitride semiconductor comprising a group III element and a group V element, and

the well layer comprises a nitride semiconductor comprising a group III element and a group V element.

11. The wafer according to claim 8, wherein

the functional layer further comprises a multilayer section provided between the first semiconductor layer and the light emitting layer,

the multilayer section comprises a plurality of high bandgap energy layers and a low bandgap energy layer provided between the plurality of high bandgap energy layers, and

a bandgap energy of the low bandgap energy layer is lower than a bandgap energy of the high bandgap energy layer.

12. The wafer according to claim 1, further comprising:

an intermediate layer provided between the buffer section and the functional layer,

wherein the intermediate layer comprises a first layer comprising a nitride semiconductor comprising Al, and a second layer provided on the first layer and comprising a nitride semiconductor having a lower Al composition ratio than the first layer.

13. The wafer according to claim 12, wherein

the intermediate layer further comprises a third layer comprising a nitride semiconductor comprising Al and provided between the first layer and the second layer, and

the Al composition ratio of the third layer is lower than the Al composition ratio of the first layer and higher than the Al composition ratio of the second layer.

14. The wafer according to claim 1, further comprising:

a foundation layer provided between the buffer section and the functional layer and comprising a nitride semiconductor,

wherein a concentration of impurity in the nitride semiconductor of the foundation layer is lower than a concentration of impurity in the nitride semiconductor of the functional layer.

15. The wafer according to claim 1, wherein

the functional layer comprises a third semiconductor layer provided on the buffer section, and a fourth semiconductor layer provided on the third semiconductor layer and forming a heterojunction with the third semiconductor layer, and

a bandgap of the fourth semiconductor layer is larger than a bandgap of the third semiconductor layer.

16. The wafer according to claim 15, wherein a lattice constant of the fourth semiconductor layer is smaller than a lattice constant of the third semiconductor layer.

17. A method for manufacturing the nitride semiconductor wafer according to claim 1, the method comprising:

forming the buffer section on the silicon substrate, and

forming the functional layer on the buffer section.

18. The wafer according to claim 1, wherein a thickness of the (i+1)-th buffer layer is set within a range where a curvature of the silicon substrate may change as the growth of the (i+1)-th buffer layer proceeds.

19. The wafer according to claim 18, wherein

a correlation between the curvature of the silicon substrate and a thickness of the silicon substrate is expressed by:

20. A nitride semiconductor device comprising:

a buffer section formed on a silicon substrate and

a functional layer provided on the buffer section and comprising a nitride semiconductor,

wherein;

the buffer section comprises first to n-th buffer layers comprising a nitride semiconductor, n being an integer of 4 or more;

an i-th buffer layer i being an integer of 1 or more and less than n, of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer;

an (i+1)-th buffer layer in direct contact with the i-th buffer layer has a lattice length W(i+1) in the first direction; and

in the first to n-th buffer layers, the i-th buffer layer and the (i+1)-th buffer layer satisfy a relation of 0.003 ≦

(W(i+1)-Wi)/Wi ≦

0.008.

21. The device according to claim 20, wherein

the major surface is a c-plane, and

the first direction is an a-axis direction.

22. The device according to claim 20, wherein

the first buffer layer comprises Al_x1Ga_1-x1N (0<

x1≦

1),

the n-th buffer layer comprises Al_xnGa_1-xnN (0≦

xn<

1), and

the i-th buffer layer between the first buffer layer and the n-th buffer layer comprises Al_xiGa_1-xiN (0<

xi<

1).

23. The device according to claim 22, wherein the Al composition ratio of the (i+1)-th buffer layer is lower than the Al composition ratio of the i-th buffer layer.

24. The device according to claim 20, wherein lattice mismatch in the first direction between the first buffer layer and the n-th buffer layer is from 1.9% to 2.5%.

25. The device according to claim 20, wherein n is 9 or less.

26. The device according to claim 20, wherein the (i+1)-th buffer layer has a relaxation of 0.65 or less.

27. The device according to claim 20, wherein the functional layer comprises:

a first semiconductor layer of a first conductivity type provided on the buffer section;

a light emitting layer provided on the first semiconductor layer; and

a second semiconductor layer of a second conductivity type provided on the light emitting layer.

28. The device according to claim 27, wherein

the light emitting layer comprises a plurality of barrier layers and a well layer provided between the plurality of barrier layers, and

a bandgap energy of the barrier layer is larger than a bandgap energy of the well layer.

29. The device according to claim 28, wherein

the barrier layers comprise a nitride semiconductor comprising a group III element and a group V element, and

the well layer comprises a nitride semiconductor comprising a group III element and a group V element.

30. The device according to claim 27, wherein

the functional layer further comprises a multilayer section provided between the first semiconductor layer and the light emitting layer,

the multilayer section comprises a plurality of high bandgap energy layers and a low bandgap energy layer provided between the plurality of high bandgap energy layers, and

a bandgap energy of the low bandgap energy layer is lower than a bandgap energy of the high bandgap energy layer.

31. The device according to claim 20, further comprising:

an intermediate layer provided between the buffer section and the functional layer,

wherein the intermediate layer comprises a first layer comprising a nitride semiconductor comprising Al, and a second layer provided on the first layer and comprising a nitride semiconductor having a lower Al composition ratio than the first layer.

32. The device according to claim 31, wherein

the intermediate layer further comprises a third layer comprising a nitride semiconductor comprising Al and provided between the first layer and the second layer, and

the Al composition ratio of the third layer is lower than the Al composition ratio of the first layer and higher than the Al composition ratio of the second layer.

33. The device according to claim 20, further comprising:

a foundation layer provided between the buffer section and the functional layer and comprising a nitride semiconductor,

wherein a concentration of impurity in the nitride semiconductor of the foundation layer is lower than a concentration of impurity in the nitride semiconductor of the functional layer.

34. The device according to claim 20, wherein

the functional layer comprises a third semiconductor layer provided on the buffer section, and a fourth semiconductor layer provided on the third semiconductor layer and forming a heterojunction with the third semiconductor layer, and

a bandgap of the fourth semiconductor layer is larger than a bandgap of the third semiconductor layer.

35. The device according to claim 34, wherein a lattice constant of the fourth semiconductor layer is smaller than a lattice constant of the third semiconductor layer.

36. The device according to claim 20, wherein a thickness of the (i+1)-th buffer layer is set within a range where a curvature of the silicon substrate may change as the growth of the (i+1)-th buffer layer proceeds.

37. The device according to claim 36, wherein

a correlation between the curvature of the silicon substrate and a thickness of the silicon substrate is expressed by: