Semiconductor device with a common back gate isolation region and method for manufacturing the same

• US 9,054,221 B2
• Filed: 11/18/2011
• Issued: 06/09/2015
• Est. Priority Date: 08/31/2011
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Liang, Qingqing, Luo, Zhijiong, Yin, Haizhou, Zhu, Huilong
• Primary Examiner(s): Nguyen, Khiem D
• Assistant Examiner(s): Vu, Pauline
• Application Number:
  US13/510,807
• Publication Number:
  US 20130049117A1
• Time in Patent Office: 1,299 Days
• Field of Search: 257/316, 257/544, 438/223, 438/224
• US Class Current: 1/1
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.

Claims

1. A semiconductor device, comprising:

an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer;

a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and

a plurality of first and second shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs,

wherein;

the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate,

a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs; and

the first shallow trench isolations are formed on the buried insulation layer; and

each of the second shallow trench isolations comprises;

a first portion extending downward into the semiconductor substrate and being configured to isolate the respective backgate of the respective adjacent MOSFETs from each other; and

a second portion extending laterally directly on the buried insulation layer and being configured to isolate the semiconductor layer of the respective adjacent MOSFETs from each other so as to define active regions of the respective adjacent MOSFETs,

wherein the first portion of the second shallow trench isolation has a width smaller than that of the second portion of the second shallow trench isolation.

2. The semiconductor device according to claim 1, wherein the respective backgate of each of the MOSFETs adjoins the buried insulation layer.

3. The semiconductor device according to claim 1, wherein the respective backgate of each of the MOSFETs is separated from the buried insulation layer.

4. The semiconductor device according to claim 1, wherein the each of the MOSFETs further comprises:

a gate stack being disposed on the semiconductor layer;

a source region and a drain region being formed in the semiconductor layer and being disposed outside the gate stack, respectively; and

a channel region being formed in the semiconductor layer and located between the source region and the drain region.

5. The semiconductor device according to claim 4, wherein the each of the MOSFETs further comprises:

source/drain conductive vias configured to be electrically connected with the source region and the drain region, respectively; and

a backgate conductive via being electrically connected with the respective backgate.

10. The semiconductor device according to claim 2, wherein the each of the MOSFETs further comprises:

a gate stack being disposed on the semiconductor layer;

a source region and a drain region being formed in the semiconductor layer and being disposed outside the gate stack, respectively; and

a channel region being formed in the semiconductor layer and located between the source region and the drain region.

11. The semiconductor device according to claim 3, wherein the each of the MOSFETs further comprises:

a gate stack being disposed on the semiconductor layer;

a source region and a drain region being formed in the semiconductor layer and being disposed outside the gate stack, respectively; and

a channel region being formed in the semiconductor layer and located between the source region and the drain region.

6. A method for manufacturing a semiconductor device, comprising:

providing an SOI wafer, which comprises a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer;

forming a plurality first and second of shallow trench isolations for isolating a plurality of MOSFETs which are to be formed adjacently to each other; and

forming the plurality of the MOSFETs in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate, wherein;

respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate,

a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs; and

the forming the plurality of the first and second shallow trench isolations comprises;

patterning the SOI wafer to form respective first portions of the second shallow trench isolations, the respective first portions each extending downward into the semiconductor substrate to a depth sufficient for isolating the respective backgate of the each of the MOSFETs from each other; and

further patterning the SOI wafer to form the first shallow trench isolations on the buried insulation and respective second portions of the second shallow trench isolations, the respective second portions each extending laterally directly on the buried insulations layer to isolate the semiconductor layer of the respective adjacent MOSFETs from each other,

wherein the respective first portions of the second shallow trench isolations have a width smaller than that of the respective second portions of the second shallow trench isolations.

7. The method according to claim 6, wherein the forming the plurality of the MOSFETs comprises:

forming the common backgate isolation region in a deep location in the semiconductor substrate by a first deep ion implantation in the semiconductor substrate with a first dopant; and

forming the respective backgate of each of the MOSFETs in a shallow location in the semiconductor substrate by a second shallow ion implantation in the semiconductor substrate with a second dopant,

wherein the second dopant has a type opposite to that of the first dopant.

8. The method according to claim 6, wherein the forming the plurality of the MOSFETs comprises:

forming respective gate stacks of the MOSFETs on the semiconductor layer; and

forming a source region and a drain region outside each of the respective gate stacks in the semiconductor layer.

9. The method according to claim 8, wherein the forming the plurality of the MOSFETs comprises:

forming source/drain conductive vias configured to be electrically connected with the source region and the drain region, respectively; and

forming backgate conductive vias, each of the backgate conductive vias being electrically connected with the respective backgates of each of the MOSFETs.

12. The method according to claim 7, wherein the forming the plurality of the MOSFETs comprises:

forming respective gate stacks of the MOSFETs on the semiconductor layer; and

forming a source region and a drain region outside each of the respective gate stacks in the semiconductor layer.