Multiple gate transistor architecture providing an accessible inner source-drain node

• US 9,064,958 B1
• Filed: 06/08/2011
• Issued: 06/23/2015
• Est. Priority Date: 05/05/2006
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Iversen, Christian Rye, Li, Jason Yuxin
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US13/156,016
• Time in Patent Office: 1,476 Days
• Field of Search: 257192-195, 257202-206, 257368-369, 257/E29.246
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/8124 with multiple gate

Abstract

The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.

Claims

1. A transistor circuit comprising:

a first multiple gate transistor comprising;

a source structure having a plurality of source fingers extending from a source bus;

a drain structure having plurality of drain fingers extending from a drain bus and interleaved with the plurality of source fingers wherein a meandering path is formed between the source and drain structures;

a plurality of gate structures that are substantially parallel with one another and extend along the meandering path between the source and drain structures, wherein at least one of the plurality of gate structures extends continuously along the meandering path;

a source-drain structure that extends along the meandering path between adjacent ones of the plurality of gate structures to form a source-drain node; and

a source-drain extension that is electrically connected to the source-drain structure and externally accessible; and

control circuitry adapted to provide control signals to corresponding one of the plurality of gate structures and to provide the source drain node via the source drain extension.

2. The transistor circuit of claim 1 further comprising a plurality of multiple gate transistors that are connected in series and include the first multiple gate transistor, wherein the control circuitry is further adapted to provide signals to source-drain structures of the plurality of multiple gate transistors is further adapted to provide control signals to gate structures of the plurality of multiple gate transistors.

3. The transistor circuit of claim 2 wherein at least one actual source-drain node is formed where any two of the plurality of multiple gate transistors are connected in series and the control circuitry is further adapted to provide a signal to the at least one actual source-drain node.

4. The transistor circuit of claim 2 wherein a source structure on a first end of the plurality of multiple gate transistors forms a first port and a drain structure on a second end of the plurality of multiple gate transistors forms a second port.

5. The transistor circuit of claim 4 wherein the first port is coupled to an antenna and the second port is coupled to at least one of a group consisting of transmitter circuitry and receiver circuitry.

6. The transistor circuit of claim 1 wherein the source structure and the drain structure are coupled between an antenna and one of a group consisting of transmitter and receiver circuitry to form an antenna switch.

7. The transistor circuit of claim 1 wherein the control circuitry is adapted to provide the control signals to disable and enable the transistor circuit, and the control circuitry is adapted to provide the signal as a DC bias signal configured to bias the first multiple gate transistor to maintain a stable input impedance for the transistor circuit.

8. The transistor circuit of claim 1 wherein the source-drain structure is continuous along a significant majority of the meandering path between the adjacent ones of the plurality of gate structures.

9. The transistor circuit of claim 1 wherein the source-drain structure is formed from a plurality of source-drain segments that are serially aligned along a significant majority of the meandering path between the adjacent ones of the plurality of gate structures, and the source-drain extension is electrically coupled to each of the plurality of source-drain segments.

10. The transistor circuit of claim 1 wherein the plurality of gate structures comprises N gate structures, there are N−

1 source-drain structures such that each of the N−

1 source-drain structures is provided between an adjacent pair of the N gate structures, and N is an integer greater than 2.

11. The transistor circuit of claim 1 wherein the source structure, the drain structure, and the plurality of gate structures form a multiple gate field effect transistor (FET).

13. The transistor circuit of claim 1 wherein the source-drain extension is externally accessible so as to facilitate electrical connections to associated circuitry, wherein at least one signal from the associated circuitry is applied to the source-drain node via the source-drain extension.

14. The transistor circuit of claim 1 wherein the at least one of the plurality of gate structures extends continuously along the meandering path comprises more than one of the plurality of gate structures extending continuously along the meandering path.

15. The transistor circuit of claim 14 wherein the more than one of the plurality of gate structures extending continuously along the meandering path comprises all of the plurality of gate structures extending continuously along the meandering path.

12. A multiple gate transistor comprising:

a source structure having a plurality of source fingers extending from a source bus;

a drain structure having plurality of drain fingers extending from a drain bus and interleaved with the plurality of source fingers wherein a meandering path is formed between the source and drain structures,

a plurality of gate structures that are substantially parallel with one another and extend along the meandering path between the source and drain structures;

a source-drain structure that extends along the meandering path between adjacent ones of the plurality of gate structures to form a source-drain node; and

a source-drain extension that is electrically connected to the source-drain structure and externally accessible to facilitate electrical connections to associated circuitry, wherein at least one signal from the associated circuitry is applied to the source-drain node via the source-drain extension, wherein at least one of the plurality of gate structures extends continuously along the meandering path;

wherein the source-drain structure is formed from a plurality of source-drain segments that are serially aligned along a significant majority of the meandering path between the adjacent ones of the plurality of gate structures, and the source-drain extension is electrically coupled to each of the plurality of source-drain segments.

16. The multiple gate transistor of claim 12 wherein the at least one of the plurality of gate structures extends continuously along the meandering path comprises more than one of the plurality of gate structures extending continuously along the meandering path.

17. The multiple gate transistor of claim 16 wherein the more than one of the plurality of gate structures extending continuously along the meandering path comprises all of the plurality of gate structures extending continuously along the meandering path.