Apparatus and method for decoding data transmissions

• US 9,075,922 B2
• Filed: 08/30/2007
• Issued: 07/07/2015
• Est. Priority Date: 09/05/2006
• Status: Active Grant

• Current Assignee: Nokia Technologies Oy (Nokia Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Madsen, Jens-Ole, Lindholm, Rune
• Primary Examiner(s): Myers, Paul R
• Application Number:
  US11/848,173
• Publication Number:
  US 20080075102A1
• Time in Patent Office: 2,868 Days
• Field of Search: 710/305
• US Class Current: 1/1
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 2213/0042 Universal serial bus [USB]

Abstract

An interface comprising a single data connection, arranged to transfer data between the user equipment and an identity module. The data transferred over the interface may be arranged to be synchronized by at least one clock signal. The data transferred over the interface may comprise universal serial bus protocol data.

Claims

1. An apparatus, comprising:

a processor; and

memory storing executable instructions that, with the processor, cause the apparatus to at least;

receive, via a data line to an identity module, a first data transmission, from the identity module, that is synchronous with a clock signal provided via a clock line between the apparatus and the identity module;

identify, from the first data transmission, a first protocol indicator that indicates a first protocol in which at least a portion of the first data transmission is being transmitted by the identity module;

decode the portion of the first data transmission based on the first protocol indicator;

receive, via the data line, a second data transmission, from the identity module, that is synchronous with the clock signal provided via the clock line;

identify, from the second data transmission, a second protocol indicator that indicates a second protocol in which at least a portion of the second data transmission is being transmitted by the identity module, wherein the second protocol is different from the first protocol; and

decode the portion of the second data transmission based on the second protocol indicator.

2. The apparatus as claimed in claim 1, wherein the first protocol is a universal serial bus (USB) protocol.

3. The apparatus as claimed in claim 1, wherein the first protocol is an asynchronous protocol.

4. The apparatus as claimed in claim 1, wherein the first protocol is a T=1 protocol.

5. The apparatus as claimed in claim 1, wherein the identity module comprises a central processing unit, read-only memory, random-access memory, and electronically erasable programmable read-only memory.

6. An apparatus as claimed in claim 1, wherein the clock signal is transmitted via the clock line from the apparatus and to the identity module.

7. An apparatus, comprising:

a processor; and

an interface in communication with the processor and an identity module, wherein the interface is configured to

provide a clock signal, via a clock line of the interface, between the processor and the identity module;

provide, via a data line of the interface between the processor and the identity module, a first data transmission that is synchronous with the clock signal, wherein the first data transmission comprises first data and a first protocol indicator that indicates a first protocol in which the first data is being provided; and

provide, via the data line, a second data transmission that is synchronous with the clock signal, wherein the second data transmission comprises second data and a second protocol indicator that indicates a second protocol in which the second data is being provided, wherein the second protocol is different from the first protocol.

8. The apparatus as claimed in claim 7, wherein the interface comprises a pull up resistor.

9. The apparatus as claimed in claim 7, wherein the first protocol indicator comprises a protocol identification byte.

10. The apparatus as claimed in claim 9, wherein a first four bits of the protocol identification byte store a value identifying the first protocol and a second four bits of the protocol identification byte store a complement of the value.

11. The apparatus as claimed in claim 7, wherein the first data transmission comprises at least one universal serial bus (USB) packet and at least one end-of-frame marker.

12. The apparatus as claimed in claim 11, wherein the USB packet is at least one of:

a Packet identifier (PID) packet;

an Address (ADDR) packet;

an end point (ENDP) packet;

a Frame number packet;

a USB data packet; and

a cyclic redundancy check (CRC) packet.

13. The apparatus as claimed in claim 7, wherein the first data transmission comprises a T=1 protocol block.

14. An apparatus, comprising:

a processor; and

memory storing executable instructions that, with the processor, cause the apparatus to at least;

receive, via a data line to a universal integrated circuit card (UICC), a first data transmission that is synchronous with a clock signal provided via a clock line between the apparatus and the UICC;

identify, from the first data transmission, a first protocol indicator that indicates a first protocol in which at least a portion of the first data transmission is being transmitted by the UICC;

decode the portion of the first data transmission based on the first protocol indicator;

receive, via the data line, a second data transmission, from the UICC, that is synchronous with the clock signal provided via the clock line;

identify, from the second data transmission, a second protocol indicator that indicates a second protocol in which at least a portion of the second data transmission is being transmitted by the UICC, wherein the second protocol is different from the first protocol; and

decode the portion of the second data transmission based on the second protocol indicator.

15. The apparatus as claimed in claim 14, wherein the first protocol indicator comprises a protocol identification byte.

16. The apparatus as claimed in claim 15, wherein a first four bits of the protocol identification byte store a value identifying the first protocol and a second four bits of the protocol identification byte store a complement of the value.

17. The apparatus as claimed in claim 14, wherein the first data transmission comprises at least one universal serial bus (USB) packet and at least one end-of-frame marker.

18. The apparatus as claimed in claim 17, wherein the at least one USB packet is at least one of:

a Packet identifier (PID) packet;

an Address (ADDR) packet;

an end point (ENDP) packet;

a Frame number packet;

a USB data packet; and

a cyclic redundancy check (CRC) packet.

19. The apparatus as claimed in claim 14, wherein the first data transmission comprises a T=1 protocol block.

20. A method comprising:

receiving, by a computing device via a data line to an identity module, a first data transmission, from the identity module, that is synchronous with a clock signal provided via a clock line between the computing device and the identity module;

identifying, from the first data transmission, a first protocol indicator that indicates a first protocol in which at least a portion of the first data transmission is being transmitted by the identity module;

decoding the portion of the first data transmission based on the first protocol indicator;

receiving, via the data line, a second data transmission, from the identity module, that is synchronous with the clock signal provided via the clock line;

identifying, from the second data transmission, a second protocol indicator that indicates a second protocol in which at least a portion of the second data transmission is being transmitted by the identity module, wherein the second protocol is different from the first protocol; and

decoding the portion of the second data transmission based on the second protocol indicator.

21. The method as claimed in claim 20, wherein the first protocol is a universal serial bus (USB) protocol.

22. The method as claimed in claim 20, wherein the first data transmission comprises an end of frame part following a predetermined size of universal serial bus (USB) protocol data.

23. The method as claimed in claim 22, wherein the predetermined size is 1500 bytes.

24. The method as claimed in claim 21, wherein USB protocol data of the first data transmission does not include SYNC packets.

25. The method as claimed in claim 21, further comprising:

filtering, by the identity module, USB protocol data of the first data transmission to remove one or more bit-stuffed logical zero signal values prior to the identity module transmitting the first data transmission to the computing device.

26. The method as claimed in claim 20, wherein the first protocol is a T=1 protocol.

27. The method of claim 20, wherein the first protocol is a T=1 protocol, and wherein the second protocol is a USB protocol.

28. A method, comprising:

receiving, by a computing device via a data line to a universal integrated circuit card (UICC), a first data transmission, from the UICC, that is synchronous with a clock signal provided via a clock line between the computing device and the UICC;

identifying, from the first data transmission, a first protocol indicator that indicates a first protocol in which at least a portion of the first data transmission is being transmitted by the UICC;

decoding the portion of the first data transmission based on the first protocol indicator;

receiving, by the computing device via the data line, a second data transmission, from the UICC, that is synchronous with the clock signal provided via the clock line;

identifying, from the second data transmission, a second protocol indicator that indicates a second protocol in which at least a portion of the second data transmission is being transmitted by the UICC, wherein the second protocol is different from the first protocol; and

decoding the portion of the second data transmission based on the second protocol indicator.

29. The method according to claim 28, wherein the first protocol is a universal serial bus (USB) protocol, and the second protocol is a T=1 protocol.

30. The method according to claim 28, wherein the first protocol is a protocol that synchronizes based on a fixed bit pattern.

31. The method according to claim 30, further comprising:

removing, by the UICC, the fixed bit pattern from first data transmission.

32. The method according to claim 28, wherein the first protocol is a protocol that is asynchronous.

33. The method according to claim 28, further comprising:

providing the at least one clock signal via the clock line between the computing device and the UICC.

34. The method according to claim 28, wherein the clock signal includes an internal clock signal of the computing device or an internal clock signal of the UICC, and the method further comprises:

transmitting, via the data line, signaling between the computing device and the UICC to synchronize the internal clock signal of the computing device and the internal clock signal of the UICC.