Non-volatile write buffer data retention pending scheduled verification

• US 9,076,530 B2
• Filed: 02/07/2013
• Issued: 07/07/2015
• Est. Priority Date: 02/07/2013
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Gomez, Kevin Arthur, Goss, Ryan James, Khoueir, Antoine, Ebsen, David Scott, Trantham, Jon D.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US13/762,033
• Publication Number:
  US 20140219034A1
• Time in Patent Office: 880 Days
• Field of Search: 365/185.22, 365/185.33
• US Class Current: 1/1
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer

Abstract

Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer. A verify circuit is adapted to perform a verify operation at the conclusion of a predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. The input write data are retained in the NV buffer until successful transfer is verified.

Claims

1. A method comprising:

storing input write data in a non-volatile (NV) buffer, the input write data having an associated logical address;

transferring a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer;

initiating a count to denote a predetermined elapsed time interval; and

performing a verify operation at responsive to the conclusion of the predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory.

2. The method of claim 1, in which the NV buffer is a rewriteable solid-state memory and the NV main memory is an eraseable solid-state memory.

3. The method of claim 2, in which the rewriteable solid-state memory is a selected one of a spin-torque random access memory (STRAM), resistive random access memory (RRAM) or a phase change random access memory (PCRAM), and the erasable solid-state memory is a flash memory.

4. The method of claim 1, in which the verify operation of the performing step is carried out responsive to an absence of an intervening write request associated with the input write data in the NV buffer during the predetermined elapsed time interval, and wherein responsive to the presence of an intervening write request associated with the input write data in the NV buffer, the verify operation is not performed.

5. The method of claim 1, further comprising transferring a copy of the input write data to a host device from the NV buffer responsive to a read request received during the elapsed time interval and prior to the verify operation, and implementing a change in cache retention policy to retain the input write data in the NV buffer after the verify operation is successfully concluded.

6. The method of claim 5, further comprising transferring a second set of data spatially and/or temporarily related to the input write data to the NV buffer responsive to the read request as a speculative data pull.

7. The method of claim 1, in which the method further comprises receiving, prior to a conclusion of the predetermined elapsed time interval, a second set of input write data having the associated logical address different from the input write data in the NV buffer, and repeating the storing, transferring, initiating and performing steps for the second set of input write data, wherein the verify operation is not performed for the input write data in the NV buffer.

8. The method of claim 1, further comprising generating a hash value using a selected hash function responsive to the input write data, storing the hash value in the NV main memory, and using the stored hash value in a subsequent write reject process involving receipt of a second set of input write data sharing the associated logical address.

9. The method of claim 1, further comprising writing the input write data using a sloppy write process responsive to a frequency of receipt of sets of input write data sharing the associated logical address.

10. The method of claim 1, wherein the predetermined elapsed time interval is a preselected, fixed amount of elapsed time so that the predetermined elapsed time interval ends upon passage of the preselected, fixed amount of elapsed time after initialization of a timer.

11. The method of claim 10, wherein the preselected, fixed amount of elapsed time is selected to exceed a relax time interval associated with the non-volatile main memory.

12. The method of claim 10, wherein the predetermined elapsed time interval is a variable amount of elapsed time which ends responsive to receipt of X access commands from a host device after the transfer of the input write data to the NV main memory, where X is a plural integer.

13. An apparatus comprising:

a non-volatile (NV) buffer adapted to store input write data having a selected logical address;

a write circuit adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer;

a timer circuit adapted to initiate a count to denote a predetermined elapsed time interval responsive to the transfer of the copy of the input write data to the NV main memory; and

a verify circuit adapted to perform a verify operation at the conclusion of the predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory.

14. The apparatus of claim 13, in which, responsive to receipt during the elapsed time interval of updated input write data having the selected logical address, the verify circuit cancels the verify operation, the NV buffer stores the updated input write data, and the write circuit transfers a copy of the updated input write data to the NV main memory.

15. The apparatus of claim 14, further comprising a hash generator which generates a hash value responsive to the updated input write data, the write circuit storing the generated hash value in the NV main memory.

16. The apparatus of claim 15, in which the verify circuit performs a verify operation upon the updated input write data responsive to a comparison of the generated hash value in the NV main memory and a second generated hash value generated responsive to the updated input write data in the NV buffer.

17. The apparatus of claim 13, further comprising a read circuit which, responsive to receipt of a read request requesting data having the selected logical address, transfers a copy of the input write data for output to a host from the NV buffer and implements a cache retention policy to retain the input write data in the NV buffer after a successful conclusion of the verify operation.

18. The apparatus of claim 13, in which the read circuit further transfers a copy of a second set of data spatially and/or temporarily related to the input write data to the NV buffer responsive to the read request as a speculative data pull.

19. The apparatus of claim 13, in which the NV main memory comprises a flash memory comprising a plurality of flash memory cells, and the write circuit further comprises a charge pump which stores the copy of the input write data to a selected set of the flash memory cells by storing accumulated charge on a floating gate structure of the selected set of the flash memory cells.

20. The apparatus of claim 19, in which the charge pump is adapted to alternatively store said accumulated charge in accordance with a fast, sloppy write process and in accordance with a slow, normal write process, and in which the charge pump stores said accumulated charge using the fast, sloppy write process responsive to a control signal indicating classification of the input write data as hot data.

21. The apparatus of claim 13, in which the NV buffer is a rewriteable solid-state memory and the NV main memory is an eraseable solid-state memory.

22. The apparatus of claim 13, in which the timer circuit denotes the predetermined elapsed time interval in terms of passage of a preselected amount of elapsed time.

23. The apparatus of claim 13, wherein the timer circuit concludes the predetermined elapsed time interval responsive to receipt of X access commands from a host device, where X is a plural integer.

24. The apparatus of claim 13, in which the predetermined elapsed time interval is varied in relation to a workload rate of received access commands.

25. An apparatus comprising:

a non-volatile (NV) buffer comprising a plurality of rewriteable non-volatile memory cells arranged as a content addressable memory (CAM) and adapted to store input write data having a selected logical address;

an NV main memory comprising a plurality of eraseable flash memory cells;

a write circuit adapted to transfer a copy of the input write data to the NV main memory while retaining the stored input write data in the NV buffer;

a timer circuit adapted to initiate demarking a predetermined elapsed time interval; and

a verify circuit which, responsive to receipt during the predetermined elapsed time interval of updated write data having the selected logical address, instructs the timer circuit to discontinue demarking of the predetermined elapsed time interval and reinitializes the timer circuit to commence demarking a second predetermined elapsed time interval for the updated write data, and wherein the verify circuit, responsive to an absence during the predetermined elapsed time interval of updated write data having the selected logical address, performs a verify operation at the conclusion of the predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory.