Semiconductor device and method of manufacturing the same

• US 9,087,735 B2
• Filed: 03/14/2013
• Issued: 07/21/2015
• Est. Priority Date: 11/16/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Ki Hong, Pyi, Seung Ho, Bin, Jin Ho
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US13/828,109
• Publication Number:
  US 20140138687A1
• Time in Patent Office: 859 Days
• Field of Search: 257/51, 438/269
• US Class Current: 1/1
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.

Claims

1. A semiconductor device, comprising:

first control gates alternately stacked with first interlayer insulating layers;

at least one selection gates alternately stacked with at least one second interlayer insulating layer on the control gates and the first interlayer insulating layers;

a first channel layer passing through the control gates and the first interlayer insulating layers and including polysilicon; and

a second channel layer formed on the first channel layer and passing through the at least one selection gate and the at least one second interlayer insulating layer, wherein the first channel layer and the second channel layer are located in different levels, an upper surface of the first channel layer contacts a lower surface of the second channel layer, and the second channel layer includes silicon germanium.

2. The semiconductor device of claim 1, wherein the first channel layer or the second channel layer has a tubular structure or a pillar structure.

3. The semiconductor device of claim 2, further comprising:

an insulating layer formed in an opening defined in the first channel layer or in the second channel layer.

4. The semiconductor device of claim 1, wherein the first channel layer includes an undoped polysilicon layer.

5. The semiconductor device of claim 1, wherein the second channel layer includes a junction doped with an impurity.

6. The semiconductor device of claim 5, wherein the junction is defined in an upper part of the second channel layer.

7. The semiconductor device of claim 5, wherein a part of the junction is located on a same level as a part of the selection gate.

8. A semiconductor device, comprising:

memory cells including a first channel layer having a polysilicon layer; and

selection transistors, each including a second channel layer connected to the first channel layer, wherein the first channel layer and the second channel layer are located in different levels, an upper surface of the first channel layer contacts a lower surface of the second channel layer, and the second channel layer includes a silicon germanium layer.

9. The semiconductor device of claim 8, wherein a content of germanium included in the second channel layer is higher than a content of germanium included in the first channel layer and threshold voltages of the selection transistors are higher than threshold voltages of the memory cells.

10. The semiconductor device of claim 8, wherein the first channel layer or the second channel layer has a tubular structure or a pillar structure.

11. The semiconductor device of claim 10, further comprising:

an insulating layer formed in an opening defined in the first channel layer or in the second channel layer having the tubular structure.

12. The semiconductor device of claim 8, wherein the first channel layer includes an undoped polysilicon layer.

13. The semiconductor device of claim 8, wherein the second channel layer includes a junction doped with an impurity.

14. The semiconductor device of claim 13, wherein a part of the junction is located on a same level as a part of a selection gate of each of the selection transistors.

15. The semiconductor device of claim 8, wherein the first and second channel layers have a tubular structure.

16. The semiconductor device of claim 15, further comprising:

a first insulating layer formed in an opening defined in the first channel layer;

a second insulating layer formed in an opening defined in a lower portion of the second channel layer; and

a junction formed in an opening defined in an upper portion of the second channel layer.

17. The semiconductor device of claim 16, wherein a part of the junction is located on a same level as a part of a selection gate of each of the selection transistors.

18. A semiconductor device, comprising:

control gates alternately stacked with first interlayer insulating layers;

at least one selection gate alternately stacked with at least one second interlayer insulating layer on the control gates and the first interlayer insulating layers;

a first channel layer passing through the control gates and the first interlayer insulating layers and including polysilicon;

a second channel layer formed on the first channel layer and passing through the at least one selection gates and the at least one second interlayer insulating layer, wherein the first channel layer and the second channel layer are located in different levels, an upper surface of the first channel layer contacts a lower surface of the second channel layer, and the second channel layer includes silicon germanium and has a tubular structure;

a first insulating layer formed in an opening defined in a lower portion of the second channel layer; and

a junction formed in an opening defined in an upper portion of the second channel layer.

19. The semiconductor device of claim 18, wherein a part of the junction is located on a same level as a part of the selection gate.

20. The semiconductor device of claim 18, further comprising:

a second insulating layer formed in an opening defined in the first channel layer.