Semiconductor device and method of manufacturing the same, and electronic apparatus

• US 9,087,760 B2
• Filed: 06/25/2013
• Issued: 07/21/2015
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Itonaga, Kazuichiro, Horiike, Machiko
• Primary Examiner(s): Tran, Sinh
• Assistant Examiner(s): Nazrul, Shahbaz
• Application Number:
  US13/926,906
• Publication Number:
  US 20130285186A1
• Time in Patent Office: 756 Days
• Field of Search: 348/294, 348/340, 348/308
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/24147 the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14647 Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A semiconductor device comprising a first semiconductor section including a first wiring layer at one side thereof, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other, a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication.

Claims

1. A semiconductor device, comprising:

a first semiconductor section including at least one first wiring layer;

a second semiconductor section including at least one second wiring layer, the first and second semiconductor sections being secured together;

a plurality of first conductive materials that extend through a device layer of the first semiconductor section to a connection point in the first wiring layer of the first semiconductor section, and a plurality of second conductive materials that extend through the first semiconductor section to a connection point in the second wiring layer of the second semiconductor section, wherein the first and second conductive materials are each arranged alternately in both of a first direction and a second direction across the first semiconductor substrate, the first and second directions being orthogonal to each other.

2. The semiconductor device of claim 1, wherein the first and second semiconductor sections are secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other.

3. The semiconductor device of claim 1, wherein the first semiconductor section and the second semiconductor section are secured by plasma bonding.

4. The semiconductor device of claim 1, wherein the first semiconductor section and the second semiconductor section are secured by an adhesive.

5. The semiconductor device of claim 1, wherein the first semiconductor section includes a pixel array.

6. The semiconductor device of claim 5, wherein the second semiconductor section includes a logic circuit.

7. The semiconductor device of claim 6, wherein the pixel array and the logic circuit are electrically connected to one another.

8. The semiconductor device of claim 7, wherein the first conductive materials connect an uppermost first wiring layer of the first semiconductor section and an uppermost second wiring layer of the second semiconductor section.

9. The semiconductor device according to claim 8, wherein a surface of the first conductive materials or the second conductive materials is connected by a trench on the first semiconductor section.

10. The semiconductor device according to claim 9, further comprising a pad connected to the first conductive material and the second conductive material.

11. The semiconductor device according to claim 10, wherein the pad is exposed at an upper side of the first semiconductor section.

12. The semiconductor device according to claim 9, wherein the trench is a Cu filled trench.

13. The semiconductor device according to claim 1,

the first wiring layer includes Cu,

the second wiring layer includes Cu.

14. The semiconductor device according to claim 1, further comprising an insulating layer covering at least part of the first wiring layer or the second wiring layer.

15. The semiconductor device according to claim 14, wherein the insulating layer is SiO.

16. The semiconductor device of claim 1, wherein the first conductive material and the second conductive material includes one of W, Al, and Au.

17. The semiconductor device of claim 7, wherein the pixel array includes a photodiode and a plurality of pixel transistors.

18. The semiconductor device of claim 7, wherein the logic circuit includes a control circuit.

19. The semiconductor device of claim 1, wherein the first conductive material and the second conductive material have substantively a same diameter.

20. The semiconductor device of claim 1, wherein the first semiconductor section has a thickness smaller than that of the second semiconductor section.

21. A semiconductor device, comprising:

a first semiconductor section including at least a first wiring layer, wherein the first semiconductor section includes a pixel array;

a second semiconductor section including at least a second wiring layer, wherein the first and second semiconductor sections are secured to one another;

a plurality of connection wirings, wherein each connection wiring in the plurality of connection wirings includes a first connection conductor interconnected to a connection pad included in the first wiring layer, a second connection conductor interconnected to a connection pad included in the second wiring layer, and a link conductor interconnecting the first and second connection conductors, and

wherein the first connection conductors and the second connection conductors of the plurality of connection wirings are alternately arranged in horizontal and vertical directions of the pixel array.

22. A semiconductor device, comprising:

a first semiconductor section including a first wiring layer;

a second semiconductor section including a second wiring layer, the first and second semiconductor sections being secured together;

a plurality of first conductive materials that extend through a device layer of the first semiconductor section to a connection point in the first wiring layer of the first semiconductor section, and a plurality of second conductive materials that extend through the first semiconductor section to a connection point in the second wiring layer of the second semiconductor section, and a pad connected to at least the first conductive materials and at least the second conductive materials, wherein the first and second conductive materials are each arranged alternately in both of a first direction and a second direction across the first semiconductor substrate, the first and second directions being orthogonal to each other.