Spinal cord stimulator system

• US 9,101,768 B2
• Filed: 03/14/2014
• Issued: 08/11/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Cirtec Medical Corp.
• Original Assignee: Globus Medical, Inc.
• Inventors: Khalil, Saif, Angara, Raghavendra, Curtis, Miles, Biele, Christopher, Fellmeth, Daniel
• Primary Examiner(s): Wieland, Robert N
• Application Number:
  US14/213,315
• Publication Number:
  US 20140277265A1
• Time in Patent Office: 515 Days
• US Class Current: 1/1
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/0551 Spinal or peripheral nerve electrodes
• CPC Class Codes: A61N 1/0553 Paddle shaped electrodes, e.g. for laminotomy
• CPC Class Codes: A61N 1/36071 Pain
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/36157 Current A61N1/3616 takes precedence
• CPC Class Codes: A61N 1/36178 Burst or pulse train parameters
• CPC Class Codes: A61N 1/36185 Selection of the electrode configuration
• CPC Class Codes: A61N 1/37217 characterised by the communication link, e.g. acoustic or tactile
• CPC Class Codes: A61N 1/37223 Circuits for electromagnetic coupling
• CPC Class Codes: A61N 1/37229 Shape or location of the implanted or external antenna
• CPC Class Codes: A61N 1/37235 Aspects of the external programmer
• CPC Class Codes: A61N 1/37241 providing test stimulations
• CPC Class Codes: A61N 1/3752 Details of casing-lead connections
• CPC Class Codes: A61N 1/3754 Feedthroughs
• CPC Class Codes: A61N 1/3787 from an external energy source

Abstract

Spinal cord stimulation (SCS) system having a recharging system with self alignment, a system for mapping current fields using a completely wireless system, multiple independent electrode stimulation outsource, and IPG control through software on Smartphone/mobile device and tablet hardware during trial and permanent implants. SCS system can include multiple electrodes, multiple, independently programmable, stimulation channels within an implantable pulse generator (IPG) providing concurrent, but unique stimulation fields. SCS system can include a replenishable power source, rechargeable using transcutaneous power transmissions between antenna coil pairs. An external charger unit, having its own rechargeable battery, can charge the IPG replenishable power source. A real-time clock can provide an auto-run schedule for daily stimulation. A bi-directional telemetry link informs the patient or clinician the status of the system, including the state of charge of the IPG battery. Other processing circuitry in current IPG allows electrode impedance measurements to be made.

Claims

1. An implantable pulse generator comprising:

a casing having an epoxy header;

a circuit board housed in the casing comprising;

a microcontroller;

a single application specific integrated circuit (ASIC) in communication with the microcontroller, the single ASIC having a combined analog and digital sections, wherein the analog section further comprises at least one pair of digital to analog converters (DAC) wherein one of the pair is a positive current DAC and the other of the pair is a negative current DAC, and wherein the ASIC generates stimulation signals;

a plurality of output capacitors;

a power management chip in electrical communication with the microcontroller; and

support circuitry;

an implantable grade lithium ion rechargeable battery housed in the casing and in electrical communication with the circuit board;

a charging coil in electrical communication with the rechargeable battery;

a RF antenna housed in the epoxy header;

a lead contact system housed in the epoxy header wherein the lead contact system provides connection for up to thirty-two leads;

a feedthrough having a plurality of pins that interface on one side with the circuit board and interface on the other side with the lead contact system and the RF antenna;

a wireless interface

wherein the wireless interface is configured to operate in the 402 MHz to 405 MHz range utilizing up to 10 channels for telemetry enabling interoperability.

2. The implantable pulse generator of claim 1, the ASIC digital section comprising:

a plurality of digital register memory elements in electrical communication with the microprocessor;

a plurality of timing generators in electrical communication with the microprocessor and in receipt of a clock signal, the clock signal fed to a counter, an output of the counter fed to a first input of each of a plurality of comparators and a second input of each of the plurality of comparators is in electrical communication with one of the plurality of digital register memory elements;

a plurality of flip-flops wherein each flip-flop is in electrical communication with an output of a predetermined combination of the plurality of comparators and wherein the plurality of flip-flops output phases of a bi-phasic pulse;

an arbitration control in electrical communication with the plurality of flip-flops and outputting a bi-phasic pulse train and wherein the arbitration control analyzes the timing generator envelope signals and permits only one signal to be active at a time; and

a pulse burst conditioner in electrical communication with the arbitration control wherein the pulse burst conditioner outputs a bursted bi-phasic pulse train and the signal is fed to a plurality of electrode logic circuits to condition and direct the bursted bi-phasic pulse train signals to the at least one pair of DACs in the analog section of the ASIC.

3. The implantable pulse generator of claim 2, wherein the at least one positive current DAC and the at least one negative current DAC are configured to not be active concurrently.

4. The implantable pulse generator of claim 2, the analog section of the ASIC further comprising:

a power level shifter to amplify an output of the positive or negative current DAC to a higher voltage;

an output current stage having an input stage and an amplification stage with feedback, wherein the input stage is in electrical communication with the output of the power level shifter and the output of input stage is fed to an input of the amplification stage wherein the feedback uses a sensing component to maintain a constant current.

5. The implantable pulse generator of claim 4, wherein the amplified signals are pulses of varying voltages but constant current flow.

6. The implantable pulse generator of claim 2, wherein the timing generator generates rising and falling edge triggers for each phase of the bi-phasic pulse.

7. The implantable pulse generator of claim 2, wherein the counter signal is based on a microcontroller clock signal, and the register signal is based on registers programmed by the microcontroller such that when the count of the counter equals a value stored in the register, the comparator outputs a positive signal.

8. The implantable pulse generator of claim 1, further comprising a magnet switch activatable by an external magnet to enable and disable the implantable pulse generator.

9. The implantable pulse generator of claim 1, wherein the lead contact system comprises:

a plurality of locking housings, each locking housing defining an aperture, the aperture configured to accept a silicone tube and the silicone tube configured to accept a lead, and wherein the locking housing further defines a second aperture configured to accept a compression lead lock mechanism; and

a plurality of lead contacts, each lead contact separated from an adjacent lead contact by a silicone seal, wherein the lead contacts are configured in stacks of up to eight lead contacts and each stack is connected at one end to one locking housing and wherein the lead contacts connect to the feedthrough.

10. The implantable pulse generator of claim 1, wherein stimulation parameters are input to the implantable pulse generator via the wireless interface.

11. The implantable pulse generator of claim 10, wherein the inputted stimulation parameters contain overhead information, a register address, data to be stored in the register, and a command byte dictating microprocessor function.

12. The implantable pulse generator of claim 1, wherein the feedthrough has at least 32 pins.

13. The implantable pulse generator of claim 1, wherein the implantable pulse generator is configured to deliver stimulus to a plurality of implantable stimulation electrodes wherein the electrodes can be grouped into stimulation sets, and the stimulation sets can be grouped into multiple channels wherein the channels have two or more stimulation sets of electrodes.

14. The implantable pulse generator of claim 13, wherein at least ten channels are activated by connecting the positive current or negative current DAC to any one of the plurality of electrodes contact or the casing to be connected to any other ones of the plurality of electrodes.

15. The implantable pulse generator of claim 14, wherein the implantable pulse generator is configured to deliver the bi-phasic electrical pulses to a plurality of implantable stimulation electrodes wherein the electrodes are grouped in stimulation sets, each stimulation set programmable with different stimulation parameters.

16. The implantable pulse generator of claim 15, wherein the plurality of implantable stimulation electrodes output a programmable constant output current of at least 12.7 mA over a range of output voltages, wherein the output voltages can be as high as 16 volts.

17. The implantable pulse generator of claim 13, wherein at least ten channels are activated by a low impedance switching matrix allowing any one of the plurality of electrodes contact or the casing to be connected to any other ones of the plurality of electrodes.

18. A method of providing an implantable pulse generator to provide stimulation to a spinal cord comprising:

implanting the implantable pulse generator subcutaneously;

implanting a plurality of implantable stimulation electrodes in the epidural space;

electrically connecting the plurality of implantable stimulation electrodes to the implantable pulse generator via a plurality of implantable leads, wherein the number of implantable leads can be up to 32;

inputting stimulation parameters on a computing device via a clinician programmer application;

communicating the stimulation parameters to the implantable pulse generator via a wireless communication device; and

delivering electrical pulses based on the stimulation parameters to the electrodes where the pulses are bi-phasic and have a constant output current of at least 12.7 mA over a range of output voltages, wherein the output voltages can be as high as 16 volts

wherein the implantable pulse generation includes a single application specific integrated circuit (ASIC) in communication with the microcontroller, the single ASIC having a combined analog and digital sections, wherein the analog section further comprises at least one pair of digital to analog converters (DAC) wherein one of the pair is a positive current DAC and the other of the pair is a negative current DAC, and wherein the ASIC generates stimulation signals.

19. A kit for delivery of stimulation to a spinal cord comprising:

an implantable pulse generator for delivering electrical pulses;

a plurality of implantable stimulation electrodes for implanting in the epidural space;

a plurality of implantable leads for electrically connecting the plurality of implantable stimulation electrodes to the implantable pulse generator;

a clinician programmer application on a computing device for inputting stimulation parameters;

a wireless communications device for communicating the stimulation parameters to the implantable pulse generator from the computing device, wherein the electrical pulses based on the stimulation parameters are provided to the electrodes where the pulses are bi-phasic and have a constant output current of at least 12.7 mA over a range of output voltages, wherein the output voltages can be as high as 16 volts

wherein the implantable pulse generation includes a single application specific integrated circuit (ASIC) in communication with the microcontroller, the single ASIC having a combined analog and digital sections, wherein the analog section further comprises at least one pair of digital to analog converters (DAC) wherein one of the pair is a positive current DAC and the other of the pair is a negative current DAC, and wherein the ASIC generates stimulation signals.