Apparatus, system, and method for destaging cached data

• US 9,104,599 B2
• Filed: 04/15/2011
• Issued: 08/11/2015
• Est. Priority Date: 12/06/2007
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Intelligent Intellectual Property Holdings LLC
• Inventors: Atkisson, David, Flynn, David
• Primary Examiner(s): Alsip, Michael
• Application Number:
  US13/088,211
• Publication Number:
  US 20110258391A1
• Time in Patent Office: 1,579 Days
• Field of Search: 711/113, 711/118, 711/133, 711/143
• US Class Current: 1/1
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2211/103 Hybrid, i.e. RAID systems with parity comprising a mix of RAID types
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/604 Details relating to cache allocation
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H05K 7/1444 Complex or three-dimensional-arrangements; Stepped or dual mother boards

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for destaging cached data. A method includes caching write in a nonvolatile solid-state cache by appending the data to a log of the nonvolatile solid-state cache. The log includes a sequential, log-based structure preserved in the nonvolatile solid-state cache. A method includes destaging at least a portion of the data from the nonvolatile solid-state cache to the backing store in a cache log order. The cache log order comprises an order in which the data was appended to the log of the nonvolatile solid-state cache.

Claims

1. A method for destaging cached data, the method comprising:

caching write data in a nonvolatile solid-state cache by appending the data to a log of the nonvolatile solid-state cache, the log comprising a sequential, log-based structure maintained on the nonvolatile solid-state cache;

determining a destaging pressure for the nonvolatile solid-state cache, the destaging pressure comprising a level of demand for destaging cached data of the nonvolatile solid-state cache; and

destaging a portion of the data from the nonvolatile solid-state cache to the backing store in a cache log order if the destaging pressure does not satisfy a threshold, the cache log order indicative of an order in which the data was appended to the log of the nonvolatile solid-state cache or

if the destaging pressure satisfies the threshold, destaging a portion of data from a non-volatile solid state cache to a backing store in a backing store address order.

2. The method of claim 1, further comprising:

adjusting a destaging rate to satisfy the destaging pressure by adjusting a ratio of data to destage in the cache log order to data to destage in the sequential backing store address order.

3. The method of claim 1, wherein the sequential backing store address order comprises one or more ranges of address contiguous data, the contiguous data in a range sequentially ordered by backing store address.

4. The method of claim 1, wherein destaging data in sequential backing store address order comprises traversing a mapping structure that maps backing store addresses to locations on physical storage media of the nonvolatile solid-state cache and selecting a destage data range such that members of the data range have contiguous and sequential backing store addresses.

5. The method of claim 1, wherein each backing store address directly maps to a logical address of the nonvolatile solid-state cache, and wherein logical addresses of the cache are independent of physical storage media addresses of the nonvolatile solid-state cache, and wherein a logical address space of the nonvolatile solid-state cache exceeds a storage capacity of the physical storage media of the nonvolatile solid-state cache.

6. The method of claim 1, wherein the nonvolatile solid-state cache comprises a lower destage rate destaging in the cache log order than destaging in the sequential backing store address order and the backing store comprises a higher write rate destaging in the sequential backing store address order than destaging in the cache log order.

7. The method of claim 1, further comprising preventing destaging of data within a predefined distance of an append point of the log of the nonvolatile solid-state cache.

8. The method of claim 1, wherein determining the destaging pressure comprises determining a difference between an actual amount of dirty write data of the nonvolatile solid-state cache and a target amount of dirty write data of the nonvolatile solid-state cache, dirty write data comprising write data cached in the nonvolatile solid-state cache that has not been destaged to the backing store.

9. The method of claim 1, wherein destaging in cache log order comprises destaging data region by region, the regions ordered in cache log order.

10. The method of claim 9, further comprising re-ordering data of a region to a backing store address order such that the regions destage in the cache log order and data within a region destages to the backing store in the backing store address order for addresses within a region.

11. The method of claim 1, wherein the log of the nonvolatile solid-state cache comprises multiple append points for writing cached data, the multiple append points comprising at least one append point for writing dirty data and at least one append point for writing clean data, dirty data comprising write data that has not been destaged to the backing store and clean data comprising data that is stored in the backing store.

17. The method of claim 1, wherein the destaged portion of the data comprises dirty write data identified as a destaging candidate.

18. The method of claim 1, wherein the cache log order comprises destaging beginning with older data and proceeding toward newer data.

19. The method of claim 1, wherein the cache log order comprises destaging beginning with newer data and proceeding toward older data.

12. An apparatus to destage cached data, the apparatus comprising:

a cache write module configured to append data to a log of a nonvolatile solid-state device, the log comprising a sequential, log-based structure; and

a destage module configured to destage at least a portion of the data from the nonvolatile solid-state device and store that portion of the data in a backing store in an order defined by ascending backing store address, the apparatus further comprising a destaging pressure module configured to determine a destaging pressure for the nonvolatile solid-state device, the destaging pressure comprising a level of demand for destaging data of the nonvolatile solid-state device;

wherein the destage module is configured to destage at least a portion of the data to the backing store in the sequential, backing store address order in response to the destaging pressure satisfying a predefined destaging pressure criteria and is configured to destage at least a portion of the data to the backing store in a cache log order in response to the destaging pressure failing to satisfy the predefined destaging pressure criteria.

13. The apparatus of claim 12, wherein the order that favors operation of the nonvolatile solid-state device comprises a cache log order, the cache log order comprising an order in which the data was appended to the log of the nonvolatile solid-state cache.

14. A computer program product comprising a non-transitory computer readable storage medium storing computer usable program code executable to perform operations for destaging cached data, the operations comprising:

determining a destaging pressure that comprises a level of demand for destaging cached data;

destaging a portion of data from a non-volatile solid state cache to a backing store in a cache log order if the destaging pressure does not satisfy a threshold, the cache log order indicative of an order in which the data was appended to a log of the non-volatile solid state cache;

or

if the destaging pressure satisfies the threshold, destaging a portion of data from a non-volatile solid state cache to a backing store in a backing store address order.

15. The computer program product of claim 14, wherein adjusting the destaging rate comprises adjusting a ratio of the portion of data destaged in the cache log order to a portion of data destaged in a sequential, backing store address order.

16. The computer program product of claim 14, wherein the operations further comprise determining the destaging pressure based on a difference between an actual amount of dirty write data of the cache that has not yet been destaged to the backing store and a target amount of dirty write data of the cache.