Super junction structure having a thickness of first and second semiconductor regions which gradually changes from a transistor area into a termination area

• US 9,112,022 B2
• Filed: 07/31/2013
• Issued: 08/18/2015
• Est. Priority Date: 07/31/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weber, Hans
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Tran, Dzung
• Application Number:
  US13/955,681
• Publication Number:
  US 20150035048A1
• Time in Patent Office: 748 Days
• Field of Search: 257/329, 257/655, 257/335, 257/200, 257/336, 257/618, 257/653, 257/E29.005, 438/268, 438/478, 438/510, 438/427
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A super junction semiconductor device includes a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. A width w₁ of the first of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w₂ of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area.

Claims

1. A super junction semiconductor device, comprising:

a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction;

each one of the first areas includes a first semiconductor region of a first conductivity type;

each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type; and

wherein

a width w₁ of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w₂ of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area.

2. The super junction semiconductor device of claim 1, further comprising a transition area between the transistor cell area and the edge termination area, wherein the widths w₁, w₂ continuously change, along the second lateral direction, from a first value in the transistor cell area to a second value in the edge termination area, respectively.

3. The super junction semiconductor device of claim 1, further comprising a transition area between the transistor cell area and the edge termination area, wherein the widths w₁, w₂ in different ones of the alternately arranged first and second areas gradually change, along the first lateral direction, from a first value in the transistor cell area to a second value in the edge termination area, respectively.

4. The super junction semiconductor device of claim 1, wherein the width w₂ of each one of the second semiconductor regions in the edge termination area ranges between 30% to 90% of the width w₂ in the transistor cell area.

5. The super junction semiconductor device of claim 1, wherein the inner area includes one or a combination of intrinsic semiconductor material, lightly doped semiconductor material, dielectric material and a void.

6. The super junction semiconductor device of claim 1, wherein each one of the first areas is a mesa region and the each one of the second areas includes a trench and the second semiconductor regions lining opposite sidewalls of the trench.

7. The super junction semiconductor device of claim 1, further comprising a transition area between the transistor cell area and the edge termination area, wherein a depth d₂ of the second semiconductor regions in different ones of the second areas decreases, along the first lateral direction, from the transistor cell area into the transition area.

8. The super junction semiconductor device of claim 1, further comprising a channel stopper structure including a doped semiconductor region electrically coupled to a field plate, wherein the second semiconductor regions extending along the second lateral direction from the transistor cell area through the edge termination area overlap with the field plate.