Current-controlled CMOS logic family

• US 9,112,487 B2
• Filed: 05/21/2010
• Issued: 08/18/2015
• Est. Priority Date: 06/28/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hairapetian, Armond
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US12/784,713
• Publication Number:
  US 20100225355A1
• Time in Patent Office: 1,915 Days
• Field of Search: 341/100, 341/101, 327/210, 327/211, 327/407, 327/408, 327/415, 327/416
• US Class Current: 1/1
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. An apparatus, comprising:

a circuit block, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, for serializing a plurality of signals thereby generating a serialized signal.

2. The apparatus of claim 1, further comprising:

a CMOS logic block, within the circuit block, for providing at least one of the plurality of signals; and

a C³MOS logic block, within the circuit block, for receiving the plurality of signals and outputting the serialized signal.

3. The apparatus of claim 1, further comprising:

a plurality of CMOS logic blocks, within the circuit block, for respectively providing the plurality of signals; and

a C³MOS logic block, within the circuit block, for receiving the plurality of signals and outputting the serialized signal.

4. The apparatus of claim 1, wherein:

each of the plurality of signals having a first frequency; and

the serialized signal having a second frequency.

5. The apparatus of claim 4, wherein:

the second frequency being greater than the first frequency.

6. The apparatus of claim 4, wherein:

the second frequency being an integer multiple of the first frequency.

7. The apparatus of claim 1, wherein:

the CMOS logic being coupled to a first power supply; and

the C³MOS logic being coupled to a second power supply.

8. The apparatus of claim 1, wherein:

the plurality of signals and the serialized signal being electrical signals including data compliant with a fiber channel.

9. The apparatus of claim 1, wherein:

the serialized signal being a differential signal.

10. The apparatus of claim 1, wherein:

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein;

a current steering circuit within the C³MOS circuit including the first source and the second source;

the first source and the second source being coupled together and to a current source; and

the first drain and the second drain being coupled to a power supply.

11. The apparatus of claim 10, wherein:

the first source and second source being coupled to at least one additional power supply via the current source.

12. The apparatus of claim 10, wherein:

the current source being coupled to at least one additional power supply.

13. The apparatus of claim 10, wherein:

current steering being performed within the current steering circuit in response to at least one of the plurality of signals, being a differential signal, being provided to the first gate and the second gate.

14. The apparatus of claim 10, wherein:

the first drain being coupled to the power supply via a first resistive load; and

the second drain being coupled to the power supply via a second resistive load.

15. An apparatus, comprising:

an input for receiving a serialized signal from a first stage; and

a second stage, including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, for processing the serialized signal, wherein;

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source;

a current steering circuit within the C³MOS circuit including the first source and the second source;

the first source and the second source being coupled together and to a current source; and

the first drain and the second drain being coupled to a power supply.

16. The apparatus of claim 15, wherein:

the first stage including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C³MOS) logic.

17. The apparatus of claim 15, wherein:

the first stage including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated.

18. The apparatus of claim 17, wherein:

the CMOS logic being coupled to a first power supply; and

the C³MOS logic being coupled to a second power supply.

19. The apparatus of claim 15, wherein:

the second stage deserializing the serialized signal thereby generating a deserialized signal including a plurality of signals.

20. The apparatus of claim 19, wherein:

the serialized signal having a first frequency; and

each of the plurality of signals having a second frequency.

21. The apparatus of claim 20, wherein:

the first frequency being greater than the second frequency.

22. The apparatus of claim 20, wherein:

the first frequency being an integer multiple of the second frequency.

23. The apparatus of claim 19, further comprising:

a third stage, coupled to the second stage, for processing the deserialized signal thereby generating at least one additional deserialized signal that includes at least one additional plurality of signals.

24. The apparatus of claim 23, wherein:

the third stage including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated.

25. The apparatus of claim 24, wherein:

the CMOS logic being coupled to a first power supply; and

the C³MOS logic being coupled to a second power supply.

26. The apparatus of claim 23, further comprising:

a fourth stage, coupled to the third stage, for serializing the at least one additional deserialized signal thereby generating at least one additional serialized signal.

27. The apparatus of claim 26, wherein:

the fourth stage including at least one additional C³MOS circuit having a third MOS transistor with a third drain, a third gate, and a third source and a fourth MOS transistor with a fourth drain, a fourth gate, and a fourth source, wherein;

at least one additional current steering circuit including the third source and the fourth source;

the third source and the fourth source being coupled together and to at least one additional current source; and

the third drain and the fourth drain being coupled to the power supply.

28. The apparatus of claim 15, wherein:

the serialized signal being an electrical signal including data compliant with a fiber channel.

29. The apparatus of claim 15, wherein:

the serialized signal being a differential signal.

30. An apparatus, comprising:

an input for receiving a serialized signal from a first stage including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated; and

a second stage, including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, for processing the serialized signal, wherein;

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source;

a current steering circuit within the C³MOS circuit including the first source and the second source;

the first source and the second source being coupled together and to a current source; and

the first drain and the second drain being coupled to a power supply; and

wherein;

the CMOS logic being coupled to a first power supply; and

the C³MOS logic being coupled to a second power supply.

31. The apparatus of claim 30, wherein:

the second stage deserializing the serialized signal thereby generating a deserialized signal including a plurality of signals.

32. The apparatus of claim 31, wherein:

the serialized signal having a first frequency; and

each of the plurality of signals having a second frequency.

33. The apparatus of claim 32, wherein:

the first frequency being greater than the second frequency.

34. The apparatus of claim 32, wherein:

the first frequency being an integer multiple of the second frequency.

35. The apparatus of claim 30, further comprising:

a third stage, coupled to the second stage, for processing the deserialized signal thereby generating at least one additional deserialized signal that includes at least one additional plurality of signals.

36. The apparatus of claim 35, wherein:

the third stage including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated.

37. The apparatus of claim 35, further comprising:

a fourth stage, coupled to the third stage, for serializing the at least one additional deserialized signal thereby generating at least one additional serialized signal.

38. The apparatus of claim 37, wherein:

the fourth stage including at least one additional C³MOS circuit having a third MOS transistor with a third drain, a third gate, and a third source and a fourth MOS transistor with a fourth drain, a fourth gate, and a fourth source, wherein;

at least one additional current steering circuit including the third source and the fourth source;

the third source and the fourth source being coupled together and to at least one additional current source; and

the third drain and the fourth drain being coupled to the power supply.

39. The apparatus of claim 30, wherein:

the serialized signal being an electrical signal including data compliant with a fiber channel.

40. The apparatus of claim 30, wherein:

the serialized signal being a differential signal.