ASIP with reconfigurable circuitry implementing atomic operations of a PLL

• US 9,116,769 B2
• Filed: 11/19/2012
• Issued: 08/25/2015
• Est. Priority Date: 09/15/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Staszewski, Roman, Staszewski, Robert B., Shi, Fuqiang
• Primary Examiner(s): Mai, Tan
• Application Number:
  US13/680,441
• Publication Number:
  US 20130080495A1
• Time in Patent Office: 1,009 Days
• Field of Search: 708/300
• US Class Current: 1/1
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 7/605 Additive or subtractive mixing of two pulse rates into one beat-frequency oscillators H03B21/00; input circuits of electric counters, e.g. up-down counters H03K21/00
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04W 56/003 Arrangements to increase tolerance to errors in transmission or reception timing

Abstract

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

Claims

1. An application specific instruction-set processor comprising:

A. an instruction memory containing atomic application specific instructions for implementing phase locked loop computations, the instruction memory having instruction outputs;

B. decoding circuitry having inputs coupled to the instruction memory outputs and having control outputs carrying control signals;

C. computational circuitry having control inputs receiving control signals coupled with the decoding circuitry control outputs and having data bus connections, the computational circuitry including arithmetic circuitry, logic circuitry, data storage circuitry, and reconfigurable circuitry, the reconfigurable circuitry implementing an atomic operation of the phase locked loop operation in response to control signals decoded from an atomic application specific instruction;

D. a data bus coupled to the data bus connections;

E. a register file and data memory having connections coupled to the data bus; and

F. interface circuitry having first connections coupled to the data bus and a tuning word output.

2. The processor of claim 1 in which one atomic application specific instruction implements an addition operation.

3. The processor of claim 1 in which one atomic application specific instruction implements an accumulation operation.

4. The processor of claim 1 in which one atomic application specific instruction implements an IIR filtering operation.

5. The processor of claim 1 in which one atomic application specific instruction implements a multiplication operation.