Data synchronization for circuit resources without using a resource buffer

• US 9,118,611 B2
• Filed: 08/22/2011
• Issued: 08/25/2015
• Est. Priority Date: 08/20/2010
• Status: Active Grant

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Mosys Incorporated (Peraso, Inc.)
• Inventors: Patel, Jay
• Primary Examiner(s): Patel, Hitesh
• Application Number:
  US13/215,205
• Publication Number:
  US 20120047260A1
• Time in Patent Office: 1,464 Days
• Field of Search: 709/214, 709/225, 709/227, 711/142, 711/154, 370/429, 370/439, 370/445, 375/356, 375/371, 375/376
• US Class Current: 1/1
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal

Abstract

A method of resource-synchronizing data that is transmitted on a communication link having at least one data lane, between a first device and a second device, wherein the second device has a resource that is accessible based on an access schedule. In one operation, a timing offset of the second device based on the access schedule is determined, followed by delaying the transmission of data from the first device to the second device through the communication link by an amount of time equal to the timing offset so that the data is received at the resource when the resource is accessible according to the access schedule.

Claims

1. A method of resource-synchronizing data transmitted on a communication link between a first device and a second device, the communication link having at least one data lane, wherein the second device has a SerDes coupled to a hardware resource that is accessible based on an access schedule, the method comprising:

determining a timing offset at which cycle the hardware resource is available in the second device based on the access schedule of the hardware resource in the second device;

communicating the timing offset to the first device, and

delaying transmission of data from the first device to the second device through the communication link by the timing offset so that the data is received at the hardware resource when the hardware resource is accessible according to the access schedule; and

wherein;

the hardware resource of the second device is inaccessible outside of the access schedule;

the access schedule indicates entry points for accessing individual portions of the hardware resource of the second device;

the access schedule is a cyclical schedule for the individual portions of the hardware resource in the second device, and wherein both the first device and the second device are synchronized to the schedule; and

the timing offset for transmission of data from the first device to the SerDes of the second device is determined so that the SerDes of the second device is capable of forwarding the data to the hardware resource according to the access schedule without a need for buffering the data between the SerDes of the second device and the hardware resource of the second device.

2. The method of claim 1, wherein the communication link is a multi-lane communication link, and link-synchronization is performed prior to the resource-synchronization.

3. The method of claim 1, wherein the access schedule of the hardware resource in the second device is programmable.

4. The method of claim 1, wherein the access schedule provides a repeating access pattern for the hardware resource of the second device.

5. The method of claim 1, wherein the access schedule is a repeating sequence that indicates when the hardware resource is available for access.

6. The method of claim 1, wherein a scheduler in the first device schedules the transmissions of data from the first device to the second device according to the access schedule of the hardware resource of the second device.

7. The method of claim 1, wherein the timing offset is a predictable delay based on the access schedule for the individual portions of the hardware resource in the second device, and wherein both the first device and the second device are synchronized to the cyclical schedule.

8. The method of claim 1, wherein the hardware resource is a memory.

9. The method of claim 1, wherein the access schedule is a fixed access schedule.

10. An apparatus comprising:

a memory that is accessible based on an access schedule;

a SerDes coupled to the memory; and

a resource synchronizer; and

wherein the apparatus is configured to;

determine a timing offset at which cycle the memory is available in the apparatus based on the access schedule of the memory;

communicate the timing offset to another device;

receive a delayed transmission of data from the other device through a communication link with the timing offset so that the data is received at the memory when the memory is accessible according to the access schedule; and

wherein;

the memory is inaccessible outside of the access schedule;

the access schedule indicates entry points for accessing individual portions of the memory of the apparatus;

the access schedule is a cyclical schedule for the individual portions of the memory in the apparatus, and wherein both the other device and the apparatus are synchronized to the cyclical schedule; and

the timing offset for transmission of data from the other device to the SerDes of the apparatus is determined so that the SerDes of the apparatus is capable of forwarding the data to the memory according to the access schedule without a need for buffering the data between the SerDes of the apparatus and the memory of the apparatus.

11. The apparatus of claim 10, wherein the memory includes a plurality of portions each of which is accessible at different times according to the access schedule.

12. The apparatus of claim 10, wherein the resource-synchronizer includes a scheduler for maintaining a plurality of partitions each corresponding to a portion of the memory.

13. The apparatus of claim 10, wherein the access schedule is a fixed access schedule based on a fixed cycle of availability of the portions of memory.

20. The apparatus of claim 10, wherein:

the timing offset is a quantity of cycles between zero and multiple cycles based upon the schedule of the memory.

14. An electronic communication system, comprising:

a first device for communicating information; and

a second device coupled to the first device via a communication link, wherein the second device comprises;

a hardware resource that is accessible based on an access schedule;

a SerDes coupled to the hardware resource; and

a resource synchronizer; and

wherein the second device is configured to;

determine a timing offset at which cycle the hardware resource is available in the second device based on the access schedule of the hardware resource;

communicate the timing offset to the first device;

receive a delayed transmission of data from the first device through the communication link with the timing offset so that the data is received at the hardware resource when the hardware resource is accessible according to the access schedule; and

wherein;

the hardware resource is inaccessible outside of the access schedule;

the access schedule indicates entry points for accessing individual portions of the hardware resource of the second device;

the access schedule is a cyclical schedule for the individual portions of the hardware resource in the second device, and wherein both the first device and the second device are synchronized to the cyclical schedule; and

the timing offset for transmission of data from the first device to the SerDes of the second device is determined so that the SerDes of the second device is capable of forwarding the data to the hardware resource according to the access schedule without a need for buffering the data between the SerDes of the second device and the hardware resource of the second device.

15. The electronic communication system of claim 14, wherein the first device includes a scheduler configured to schedule transmission of data from the first device to the second device according to the access schedule.

16. The electronic communication system of claim 14, wherein the second device communicates an offset to the first device for synchronizing the first device with the hardware resource on the second device based on the access schedule of the hardware resource.

17. The electronic communication system of claim 14 further comprising:

a plurality of first devices coupled to the second device; and

wherein the hardware resource of the second device is divided into partitions, each accessible according to the access schedule, and wherein the second device is configured to determine respective offsets for each link to the hardware resource based on the access schedule and communicate the offsets to the plurality of first devices.

18. The electronic communication system of claim 14, wherein the hardware resource of the second device is shared by a plurality of first devices, and the access schedules communicated in parallel to the plurality of first devices, and respective offsets are sent to the plurality of first devices.

19. The electronic communication system of claim 14, wherein the access schedule is a fixed access schedule.