Memory device for a hierarchical memory architecture

• US 9,123,409 B2
• Filed: 06/11/2009
• Issued: 09/01/2015
• Est. Priority Date: 06/11/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Eilert, Sean, Leinwander, Mark
• Primary Examiner(s): DUDEK JR, EDWARD J
• Application Number:
  US12/483,198
• Publication Number:
  US 20100318718A1
• Time in Patent Office: 2,273 Days
• Field of Search: 711/117, 711/103, 711/E12.016, 709/52
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.

Claims

1. A hierarchical memory device, comprising:

a Phase Change Memory (PCM) array;

multiple interfaces having different memory formats, the multiple interfaces including a NAND interface and a mass storage device interface;

at least one processor core to perform multi-core NAND management and autonomous computing functions, the NAND management functions being configured to adjust data input/output between the NAND interface and a buffer memory coupled to the NAND interface based on extracted control and operational information including received command sets and addresses of memory devices coupled to the hierarchical memory device, the at least one processor further to interpret the received command sets and issue memory commands; and

at least one input port and a plurality of output ports such that the hierarchical memory device is simultaneously connectable in both a daisy-chain hierarchy and a hierarchical tree structure with other hierarchical memory devices and to switch traffic between the at least one input port and one of the plurality of output ports to reduce round-trip latency to a lowest layer of the hierarchical tree structure, the plurality of output ports configured to communicatively couple to at least one NAND memory external to the hierarchical memory device, the NAND interface configured to control communications between the PCM array and the at least one NAND memory such that the PCM array can cache data received from the at least one NAND memory, the at least one input port and the plurality of output ports being configurable by the at least one processor core.

2. The hierarchical memory device of claim 1, wherein the multiple interfaces further include at least one of a Random Access Memory (RAM) interface, a network interface, a storage interface or a peripheral interface.

3. The hierarchical memory device of claim 1, wherein the at least one processor core is further configured to operate the hierarchical memory device as an IO mapped, memory mapped, or memory mapped IO device.

4. The hierarchical memory device of claim 1, wherein the at least one processor core is further configured to interpret traffic in the daisy-chain hierarchy to determine whether the traffic is for the hierarchical memory device or for a downstream/upstream node.

5. The hierarchical memory device of claim 1, wherein the at least one input port is configured to communicatively couple to at least one Random Access Memory (RAM) external to the hierarchical memory device.

6. A hierarchical memory device, comprising:

a Phase Change Memory (PCM) array;

a processor core to execute algorithms for wear leveling, caching, error detection and correction, and data manipulation to precondition sections of memory having a slower state to manage performance and reliability;

at least one input port and at least one output port to connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure, the at least one output port configured to communicatively couple to at least one NAND memory external to the hierarchical memory device; and

a NAND interface configured to control communications between the PCM array and the at least one NAND memory such that the PCM array can cache data received from the at least one NAND memory, the processor core being further configured to perform multi-core NAND management and autonomous computing functions, the NAND management functions being configured to adjust data input/output between the NAND interface and a buffer memory coupled to the NAND interface based on extracted control and operational information including received command sets and addresses of memory devices coupled to the hierarchical memory device, the at least one processor further to interpret the received command sets and issue memory commands, the command sets including copy and move commands.

7. The hierarchical memory device of claim 6 wherein the hierarchical memory device operates as a sector based device.

8. The hierarchical memory device of claim 6 wherein the hierarchical memory device is connected with other hierarchical memory devices in a daisy-chain configuration.

9. The hierarchical memory device of claim 6 wherein the hierarchical memory device is connected with other hierarchical memory devices in a tree structure.

10. The hierarchical memory device of claim 6, wherein the hierarchical memory device is configurable to operate as an input/output (IO) mapped, memory mapped, or memory mapped IO device.

11. A hierarchical memory device, comprising:

a Phase Change Memory (PCM) array;

a RAM interface;

a NAND interface to extract command information to adjust a data rate with the NAND interface based on the command information, the NAND interface configured to control communications between the PCM array and at least one NAND memory external to the hierarchical memory device such that the PCM array can cache data received from the at least one NAND memory, and the NAND interface configured to couple to an output port of the hierarchical memory device;

a network interface to support signaling rates and data packet transmissions over communication links;

at least one processor core to perform multi-core NAND management and autonomous computing functions, the NAND management functions being configured to adjust data input/output between the NAND interface and a buffer memory coupled to the NAND interface based on extracted control and operational information including received command sets and addresses of memory devices coupled to the hierarchical memory device, the at least one processor further to interpret the received command sets and issue memory commands; and

a storage interface.

12. The hierarchical memory device of claim 11 wherein the RAM interface provides communication between a host and the memory device as a Double-Data-Rate Random Access Memory (DDR RAM).

13. The hierarchical memory device of claim 11 wherein the RAM interface provides communication between a host and the memory device as a Double-Data-Rate three Synchronous Dynamic Random Access Memory (DDR3 SDRAM).

14. The hierarchical memory device of claim 11 wherein the RAM interface is a reduced power Low Power Double-Data-Rate (LPDDR) interface.

15. The hierarchical memory device of claim 11 wherein the NAND interface operates as a sector based interface.

16. The hierarchical memory device of claim 11 wherein the network interface supports an Ethernet protocol.

17. The hierarchical memory device of claim 11 wherein the network interface supports an InfiniBand point-to-point bidirectional serial link.

18. The hierarchical memory device of claim 11 wherein the network interface supports Institute of Electrical and Electronics Engineers 802.11 communication links.

19. The hierarchical memory device of claim 11 wherein the storage interface is a Serial ATA (SATA) storage interface that allows communication between a host bus and mass storage devices.

20. The hierarchical memory device of claim 11 wherein the storage interface is a Serial-Attached SCSI (SAS) that is a point-to-point serial interface that links memory device to a disk drive.

21. The hierarchical memory device of claim 11 wherein the storage interface supports a Fibre Channel Protocol (FCP).

22. The hierarchical memory device of claim 11, further comprising a peripheral interface.

23. A packaged memory device, comprising:

at least one hierarchical memory device having one or more Phase Change Memory (PCM) arrays, one or more output ports and multiple interfaces to handle different memory formats, the multiple interfaces including a NAND interface;

at least one NAND device external to the at least one hierarchical memory device and connected to a corresponding one of the one or more output ports of the at least one hierarchical memory device, the NAND interface configured to control communications between the one or more PCM arrays and the at least one NAND device such that the one or more PCM arrays can cache data received from the at least one NAND device; and

at least one processor core to perform multi-core NAND management and autonomous computing functions, the NAND management functions being configured to adjust data input/output between the NAND interface and a buffer memory coupled to the NAND interface based on extracted control and operational information including received command sets and addresses of memory devices coupled to the hierarchical memory device, the at least one processor further to interpret the received command sets and issue memory commands.

24. The packaged memory device of claim 23, further comprising at least one Random Access Memory (RAM) having address ports and data ports in common with the at least one hierarchical memory device.

25. A memory device, comprising:

a processor core to execute algorithms for wear leveling, caching, error detection and correction, and data manipulation to precondition sections of memory having a slower state to manage performance and reliability;

at least one memory array including one or more Phase Change Memory (PCM) arrays;

multiple interfaces to handle different memory formats, the multiple interfaces including a NAND interface;

at least one input port; and

a plurality of output ports configured to communicatively couple to one or more NAND devices external to the memory device, the NAND interface configured to control communications between the one or more PCM arrays and the one or more NAND devices such that the one or more PCM arrays can cache data received from the one or more NAND devices, the least one input port and the plurality of output ports further configured such that the hierarchical memory device is connectable in either a daisy-chain hierarchy or a hierarchical tree structure with other hierarchical memory devices and to switch traffic between the at least one input port and one of the plurality of output ports to reduce round-trip latency to a lowest layer of the hierarchical tree structure.

26. The memory device of claim 25, wherein the at least one memory array further comprises at least one of a Magnetic Random Access Memory (MRAM) array or a Ferroelectric Random Access Memory (FRAM) array.

27. A memory device, comprising:

at least one memory array including one or more Phase Change Memory (PCM) arrays;

multiple interfaces to handle different memory formats, the multiple interfaces including a NAND interface;

at least one input port and at least one output port, the at least one input port configured to communicatively couple to one or more Random Access Memories (RAMs) external to the memory device and the at least one output port configured to communicatively couple to one or more NAND devices external to the memory device, the NAND interface configured to control communications between the one or more PCM arrays and the one or more NAND devices such that the one or more PCM arrays can cache data received from the one or more NAND devices; and

at least one processor core to perform multi-core NAND management and autonomous computing functions, the NAND management functions being configured to adjust data input/output between the NAND interface and a buffer memory coupled to the NAND interface based on extracted control and operational information including received command sets and addresses of memory devices coupled to the hierarchical memory device, the at least one processor further to interpret the received command sets and issue memory commands.

28. The memory device of claim 27, wherein at least one of the one or more Random Access Memories (RAMs) includes address ports and data ports in common with the memory device.