Channel, system and method for monitoring voltages

• US 9,127,987 B2
• Filed: 06/30/2010
• Issued: 09/08/2015
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Greenlight Innovation Corporation (Algonquin Power & Utilities Corp.)
• Original Assignee: Greenlight Innovation Corporation (Algonquin Power & Utilities Corp.)
• Inventors: Leung, Henry Hon-Yiu, Schneider, Mathieu Garret, Sadaghdar, Mehdi, Kazemir, Steven Scott, Pyner, Derek John, Olfert, Mark Randall, Wu, Steve Zu-Ching
• Primary Examiner(s): HWANG, TIMOTHY
• Application Number:
  US13/381,033
• Publication Number:
  US 20120101756A1
• Time in Patent Office: 1,896 Days
• US Class Current: 1/1
• CPC Class Codes: G01K 1/026 arrangements for monitoring a plurality of temperatures, e.g. by multiplexing
• CPC Class Codes: G01K 7/021 Particular circuit arrangements G01K7/026, G01K7/12, G01K7/14 take precedence
• CPC Class Codes: G01K 7/13 Circuits for cold-junction compensation
• CPC Class Codes: G01R 31/396 Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery

Abstract

Described herein are a channel, system and method for monitoring voltages. Typically, the system includes multiple channels, each for sampling one of the voltages. The channels are physically and electrically coupled to a back end board on which is mounted a field programmable gate array (FPGA) that instructs the channels to simultaneously sample the voltages. Optionally, the channel is powered using an power supply that is isolated from the back end board, and transmits information over an electrically isolated connection to the back end board. The channel also includes voltage signal processing circuitry for processing the voltage signal on board the channel, and has stored on it channel identification information composed of at least one of an operating mode of the channel and a serial number of the channel, which can assist with voltage signal processing.

Claims

1. A system for monitoring a plurality of voltage signals, the system comprising:

(a) a plurality of channels, at least one of the plurality of channels comprising;

(i) a pair of terminals comprising a reference terminal and a measurement terminal, the voltage signal measurable at the measurement terminal relative to the reference terminal;

(ii) voltage signal processing circuitry electrically coupled to the pair of terminals to receive and process the voltage signal, the voltage signal processing circuitry comprising a memory having encoded thereon channel identification information comprising at least one of an operating mode of the channel and a serial number of the channel; and

(iii) an isolation block comprising an isolator having an input and an output that are electrically isolated from each other, the isolator input electrically coupled to the voltage signal processing circuitry to receive the voltage signal and the channel identification information and then to output the voltage signal and the channel identification information to the isolator output

(b) a back end board for monitoring the plurality of voltage signals, the back end board comprising;

(i) a plurality of slots, each of the slots configured to be physically and electrically detachably coupled to one of the channels; and

(ii) voltage sampling circuitry electrically coupled to the plurality of slots and configured to communicate with the plurality of channels such that the plurality of channels simultaneously sample the plurality of voltage signals.

2. A system as claimed in claim 1 wherein the voltage signal processing circuitry comprises:

(a) an analog-to-digital converter configured to digitize and then to output a digitized voltage signal; and

(b) a microprocessor electrically coupled to the analog-to-digital converter and the memory to receive the digitized voltage signal and the channel identification information,

wherein the isolator input is electrically coupled to the microprocessor to receive the digitized voltage signal and the channel identification information and then to output the digitized voltage signal and the channel identification information to the isolator output.

3. A system as claimed in claim 2 wherein the microprocessor is configured to linearly correct for one or both of gain factor and offset errors in the digitized voltage signal and then to output a corrected voltage signal to the isolator input, and wherein the isolator outputs the corrected voltage signal to the isolator output.

4. A system as claimed in claim 3 wherein the microprocessor linearly corrects for errors in the digitized voltage signal by setting the corrected voltage signal to (the digitized voltage signal)*(the gain factor) +(the offset).

5. A system as claimed in claim 1 further comprising a current to voltage converter electrically coupled between the reference and measurement terminals, the voltage signal resulting from a current signal flowing through the current to voltage converter.

6. A system as claimed in claim 5 further comprising mode selection circuitry electrically coupled to the microprocessor and operable to indicate the operating mode, wherein the operating mode indicates whether the voltage signal results from the current signal flowing through the current to voltage converter.

7. A system as claimed in claim 6 wherein the operating mode further indicates an expected voltage range of the voltage signal.

8. A system as claimed in claim 6 wherein the operating mode further indicates whether the channel is configured to receive data transmitted using fully differential signalling.

9. A system as claimed in claim 6 wherein the mode selection circuitry comprises a voltage divider configurable to output different voltages each indicative of the operating mode of the channel.

10. A system as claimed in claim 2 further comprising an isolated power supply electrically coupled to the voltage signal processing circuitry and the isolation block, and wherein the voltage signal processing circuitry and the isolation block are powered with the isolated power supply.

11. A system as claimed in claim 10 wherein the isolated power supply comprises:

(a) a secondary winding of a transformer configured to be inductively coupled to a primary winding of the transformer, the secondary winding of the transformer configured to output a pulse train when the primary winding is electrically coupled to a voltage source outputting the pulse train;

(b) a voltage rectifier electrically coupled to the secondary winding and configured to rectify the pulse train and to output a direct-current signal;

(c) a voltage regulator electrically coupled to the voltage rectifier and to the voltage signal processing circuitry and configured to supply power to the voltage signal processing circuitry; and

wherein the primary winding of the transformer is disposed on the back end board and is inductively coupled to the secondary winding of the transformer when the at least one of the plurality of channels is physically and electrically coupled into one of the plurality of slots.

12. A system as claimed in claim 11 further comprising a precision voltage reference electrically coupled to the voltage regulator, wherein the precision voltage reference outputs a first reference voltage used to bias the reference terminals.

13. A system as claimed in claim 12 wherein the microprocessor is configured to switch between the digitized voltage signal, the first reference voltage, and a second reference voltage, wherein the first reference voltage and the second reference voltage are known values, and wherein the microprocessor is configured to calculate the gain factor and offset by:

(a) measuring the first reference voltage to obtain a measured first reference voltage, wherein the measured first reference voltage equals the gain factor multiplied by the first reference voltage plus the offset;

(b) measuring the second reference voltage to obtain a measured second reference voltage, wherein the measured second reference voltage equals the gain factor multiplied by the second reference voltage plus the offset; and

(c) solving for the gain factor and the offset using the measured reference voltages and the known values of the reference voltages.

14. A system as claimed in claim 1 wherein the voltage sampling circuitry comprises a field programmable gate array (FPGA).

15. A system as claimed in claim 2 wherein the voltage sampling circuitry comprises a FPGA and the back end board further comprises:

(a) a microcontroller electrically coupled to the FPGA and configured to receive the voltage signals from the FPGA, to condition the voltage signals such that they are suitable for network transmission, and to output the voltage signals; and

(b) a network bus having an input and an output, the network bus input electrically coupled to the microcontroller and configured to receive the voltage signals from the microcontroller and to convey the voltage signals to the network bus output.

16. A system as claimed in claim 1 wherein each of the slots comprises electrically conductive reference and measurement connectors each respectively configured to electrically mate with the reference and measurement terminals of one of the channels, and wherein the measurement connector of one of the slots is electrically coupled to the reference connector of an adjacent slot that is adjacent to the one of the slots.

17. A system as claimed in claim 1 wherein the slots are socketized to facilitate coupling and removal of the channels from the board.

18. A system as claimed in claim 15 wherein the microcontroller is configured to mitigate non-linear errors in any one of the voltage signals by applying a quadratic correction formula to the voltage signal prior to outputting it to the network bus output.

19. A system as claimed in claim 15 further comprising an off-board processor electrically coupled to the network bus output, the off-board processor electrically coupled to an off-board memory having stored thereon statements and instructions for causing the off-board processor to execute a method comprising:

(a) obtaining the channel identification information for at least one of the channels;

(b) generating a current state manifest comprising a position of the at least one of the channels on the back end board and the channel identification information of the at least one of the channels.

20. A system as claimed in claim 19 wherein the method further comprises:

(a) associating, with the at least one of the channels, calibration data associated with the serial number of the at least one of the channels; and

(b) utilizing the calibration data to mitigate errors in the voltage signals received from the at least one of the channels.

21. A system as claimed in claim 20 wherein the calibration data comprises a plurality of data points relating a listing of different digitized voltage signals to a listing of different first reference voltages, and wherein the method further comprises:

(a) determining an interpolated reference voltage to be used when measuring the voltage signal by;

(i) selecting two digitized voltage signals from the listing of different voltage signals that are closest to the digitized voltage signal; and

(ii) determining the interpolated reference voltage from the different first reference voltages related to the two digitized voltage signals; and

(b) determining the voltage signal using the interpolated reference voltage instead of the first reference voltage.

22. A system as claimed in claim 19 further comprising a display electrically coupled to the off-board processor and wherein the method further comprises:

(a) determining whether the current state manifest differs from a stored, previous state manifest;

(b) when the current state manifest differs from the previous state manifest, displaying a prompt on the display to determine whether the current state manifest is acceptable; and

(c) when the current state manifest is acceptable, overwriting the stored, previous state manifest with the current state manifest.

23. A system as claimed in claim 19 further comprising a display electrically coupled to the off-board processor and wherein the method further comprises:

(a) determining when the current state manifest comprises an invalid arrangement of channels; and

(b) when the current state manifest comprises the invalid arrangement of channels, displaying a warning on the display.

24. A system as claimed in claim 23 wherein the invalid arrangement of channels comprises one of the channels being electrically coupled to one of the slots and configured to receive data transmitted using fully differential signalling, and another one of the channels being electrically coupled to another slot that is adjacent to the one of the slots.

25. A system as claimed in claim 23 wherein the invalid arrangement of channels comprises one of the channels being electrically coupled to one of the slots and configured to measure voltage signals falling within a first voltage range, and another one of the channels being electrically coupled to another slot that is adjacent to the one of the slots and configured to measure voltage signals falling with a second voltage range that differs from the first voltage range.

26. A system as claimed in claim 15 further comprising a plurality of temperature sensors disposed on the back end board and electrically coupled to the microcontroller, and wherein the microcontroller linearly interpolates a temperature reading of a location on the back end board between the plurality of temperature sensors to perform cold junction compensation when the operating mode of the at least one of the plurality of channels is that of a thermocouple.

27. A method for monitoring a voltage signal, the method comprising:

(a) sampling the voltage signal using a channel;

(b) isolating and then outputting the voltage signal and channel identification information stored on the channel;

(c) processing the voltage signal in accordance with the channel identification information, the channel identification information comprising at least one of an operating mode of the channel and a serial number of the channel;

(d) digitizing the voltage signal to create a digitized voltage signal;

(e) linearly correcting for one or both of gain factor and offset errors in the digitized voltage signal and then outputting a corrected voltage signal;

(f) simultaneously sampling the corrected voltage signal and additional corrected voltage signals from additional channels using a field programmable gate array (FPGA);

(g) conditioning the corrected voltage signals such that they are suitable for network transmission; and

(h) outputting the corrected voltage signals to a network bus.

28. A method for monitoring a voltage signal, the method comprising:

(a) sampling the voltage signal using a channel;

(b) isolating and then outputting the voltage signal and channel identification information stored on the channel;

(c) processing the voltage signal in accordance with the channel identification information, the channel identification information comprising at least one of an operating mode of the channel and a serial number of the channel;

(d) digitizing the voltage signal to create a digitized voltage signal;

(e) linearly correcting for one or both of gain factor and offset errors in the digitized voltage signal and then outputting a corrected voltage signal;

(f) associating, with the channel, calibration data associated with the serial number of the channel, wherein the calibration data comprises a plurality of data points relating a listing of different digitized voltage signals to a listing of different first reference voltages;

(g) utilizing the calibration data to mitigate errors in the digitized voltage signal;

(h) determining an interpolated reference voltage to be used when measuring the voltage signal by;

(i) selecting two digitized voltage signals from the listing of different voltage signals that are closest to the digitized voltage signal; and

(ii) determining the interpolated reference voltage from the different first reference voltages related to the two digitized voltage signals; and

(i) determining the voltage signal using the interpolated reference voltage instead of the first reference voltage.

29. A method for monitoring a voltage signal, the method comprising:

(a) sampling the voltage signal using a channel;

(b) isolating and then outputting the voltage signal and channel identification information stored on the channel;

(c) processing the voltage signal in accordance with the channel identification information, the channel identification information comprising at least one of an operating mode of the channel and a serial number of the channel;

(d) generating a current state manifest comprising a position of the channel and the channel identification information of the channel;

(e) determining whether the current state manifest differs from a stored, previous state manifest;

(f) when the current state manifest differs from the previous state manifest, displaying a prompt to determine whether the current state manifest is acceptable; and

(g) when the current state manifest is acceptable, overwriting the stored, previous state manifest with the current state manifest.

30. A method for monitoring a voltage signal, the method comprising:

(a) sampling the voltage signal using a channel;

(b) isolating and then outputting the voltage signal and channel identification information stored on the channel;

(c) processing the voltage signal in accordance with the channel identification information, the channel identification information comprising at least one of an operating mode of the channel and a serial number of the channel;

(d) generating a current state manifest comprising a position of the channel and the channel identification information of the channel;

(e) determining when the current state manifest comprises an invalid arrangement of channels; and

(f) when the current state manifest comprises the invalid arrangement of channels, displaying a warning.

31. A method as claimed in claim 30 wherein the invalid arrangement of channels comprises one of the channels being electrically coupled to one of the slots and configured to receive data transmitted using fully differential signalling, and another one of the channels being electrically coupled to another slot that is adjacent to the one of the slots.

32. A method as claimed in claim 30 wherein the invalid arrangement of channels comprises one of the channels being electrically coupled to one of the slots and configured to measure voltage signals falling within a first voltage range, and another one of the channels being electrically coupled to another slot that is adjacent to the one of the slots and configured to measure voltage signals falling with a second voltage range that differs from the first voltage range.