Contactless wafer probing with improved power supply

• US 9,134,368 B2
• Filed: 05/07/2012
• Issued: 09/15/2015
• Est. Priority Date: 05/07/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Yung-Hsin, Huang, Po-Yi
• Primary Examiner(s): Koval, Melissa
• Assistant Examiner(s): MILLER, DANIEL R
• Application Number:
  US13/465,142
• Publication Number:
  US 20130293253A1
• Time in Patent Office: 1,226 Days
• Field of Search: 32475016-76206, 324/757.04, 324/754.21, 257/48, 438 14- 18
• US Class Current: 1/1
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Some embodiments relate to an integrated circuit. The integrated circuit includes an inductive or capacitive wireless communication structure located on a die region of the integrated circuit. This wireless communication structure is configured to wirelessly receive a test stimulus vector to test circuitry on the die region. The integrated circuit also includes a landing region having a size and location suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact with the landing region. The landing region provides a DC power supply to the circuitry on the die region while the test stimulus vector is wirelessly received.

Claims

1. An integrated circuit disposed on a semiconductor substrate, comprising:

an inductive or capacitive wireless communication structure located on a die region of the integrated circuit and configured to wirelessly receive a test stimulus vector to test circuitry on the die region; and

a plurality of landing regions located on the die region and buried at different layers having different respective heights as measured from an uppermost surface of the semiconductor substrate, wherein the respective landing regions have sizes and locations suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact therewith to provide a DC power supply to the circuitry on the die region at various stages during manufacture of the integrated circuit while the test stimulus vector is wirelessly received.

2. The integrated circuit of claim 1, wherein a landing region is located on an exposed surface of the die region.

3. The integrated circuit of claim 1, wherein a landing region is located in an internal and un-exposed region of the die region.

4. The integrated circuit of claim 3, wherein the landing region is adapted to provide power to a device structure on the die region prior to dicing of the semiconductor substrate.

5. The integrated circuit of claim 2, further comprising:

an integrated circuit package around the die region to protect the die region.

6. The integrated circuit of claim 5, wherein a pin or contact of the integrated circuit package is coupled to a landing region to provide DC power to the circuitry of the die region.

7. A semiconductor wafer, comprising:

a plurality of die regions, wherein respective die regions include respective integrated circuit structures corresponding thereto;

scribe lines arranged on the semiconductor wafer between neighboring die regions;

a power bus arranged in a scribe line on the semiconductor wafer and extending continuously between two or more of the plurality of die regions to concurrently couple a DC power supply to the two or more of the plurality of die regions; and

respective inductive or capacitive communication structures arranged on respective die regions;

wherein an inductive or capacitive communication structure on a die region is configured to wirelessly receive a test stimulus vector to an integrated circuit structure on the die region.

8. The semiconductor wafer of claim 7, wherein an inductive or capacitive communication structure on a die region is configured to wirelessly transmit a test stimulus result corresponding to a test stimulus vector applied to an integrated circuit structure on the die region.

9. The semiconductor wafer of claim 7, further comprising:

a landing region having a size and location suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact with the landing region to provide a DC power supply to one or more die regions on the semiconductor wafer while the test stimulus vector is wirelessly received.

10. The semiconductor wafer of claim 9, wherein, after the die region is diced from a semiconductor wafer, the landing region is located on an exposed surface of the die region.

11. The semiconductor wafer of claim 7, wherein, after the die region is diced from a semiconductor wafer, the landing region is located in an internal and un-exposed region of the die region.

12. The semiconductor wafer of claim 7, further comprising:

a plurality of landing regions buried at different layers having different respective heights as measured from an uppermost surface of the semiconductor wafer.

13. The semiconductor wafer of claim 12, wherein the respective landing regions have sizes and locations suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact therewith.

14. The semiconductor wafer of claim 12, wherein the landing regions are coupled to respective die regions on the semiconductor wafer to provide a DC power supply to the respective die regions while the test stimulus vector is wirelessly received.

15. A method of automated testing for a semiconductor wafer, comprising:

placing a conductive power conduit in physical and electrical contact with a power bus on the wafer, wherein the power bus is arranged in a scribe line, which separates neighboring rows or neighboring columns of integrated circuit structures from one another, and wherein the power bus extends continuously between multiple integrated circuit structures on the wafer to electrically couple the multiple integrated circuit structures to one another;

concurrently supplying a DC power to the multiple integrated circuit structures on the wafer via the conductive power conduit and the power bus; and

while the DC power is supplied to the integrated circuit structures, wirelessly transmitting stimulus test vectors to wireless communication structures on the integrated circuit structures to test functionality of the integrated circuit structures.

16. The method of claim 15, further comprising:

while the DC power is supplied to the integrated circuit structures, wirelessly receiving stimulus results, which are based on the stimulus test vectors, and which are indicative of the functionality of the integrated circuit structures.

17. The method of claim 15, wherein wireless transmission comprises radio frequency (RF) transmission, optical transmission, or ultrasonic transmission.