QoS-aware scheduling

• US 9,135,072 B2
• Filed: 09/04/2013
• Issued: 09/15/2015
• Est. Priority Date: 09/16/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Biswas, Sukalpa, Chen, Hao
• Primary Examiner(s): Sun, Michael
• Application Number:
  US14/017,971
• Publication Number:
  US 20140006743A1
• Time in Patent Office: 741 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 9/5033 considering data affinity

Abstract

In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

Claims

1. A method comprising:

receiving a plurality of memory operations in a memory controller, wherein each memory operation of the plurality of memory operations has an associated quality of service (QoS) parameter indicating a requested quality of service for performance of the memory operation to a memory controlled by the memory controller; and

grouping the plurality of memory operations into a plurality of affinity groups, wherein the memory operations within a given affinity group consume less memory bandwidth when scheduled as a group than when scheduled separately, and wherein the memory controller comprises a plurality of memory channel controllers, wherein each memory channel controller is configured to control an independent memory channel to the memory, and each memory channel controller independently grouping memory operations into affinity groups from the memory operations within a corresponding memory channel; and

scheduling memory operations directed to each memory channel of the plurality of memory channels by each memory channel controller, wherein the scheduling in a given memory channel by a given memory channel controller is responsive to the QoS parameters associated with the memory operations in the given memory channel, a state of the memory controller, and sizes of the plurality of affinity groups in the given memory channel.

2. The method as recited in claim 1 wherein the grouping comprises grouping ones of the plurality of memory operations that are page hits with each other into one of the plurality of affinity groups.

3. The method as recited in claim 1 wherein the grouping comprises grouping ones of the plurality of memory operations that are bank misses with each other into one of the plurality of affinity groups.

4. The method as recited in claim 1 wherein the grouping comprises grouping ones of the plurality of memory operations that are rank misses with each other into one of the plurality of affinity groups.

5. The method as recited in claim 1 wherein the scheduling comprises prioritizing larger affinity groups over smaller affinity groups.

6. The method as recited in claim 5 wherein the scheduling further comprises prioritizing a first affinity group having an oldest memory operation with a selected QoS parameter over other affinity groups, wherein the selected QoS parameter is determined responsive to a state of the memory controller.

7. The method as recited in claim 6 wherein the QoS parameter is eliminated for write memory operations, and wherein write affinity groups of the plurality of affinity groups are scheduled based on size of the affinity groups only.

8. The method as recited in claim 6 wherein the scheduling further comprises scheduling a largest affinity group of the plurality of affinity groups responsive to no affinity groups of the plurality of affinity groups having the selected QoS parameter.

9. A memory controller in an integrated circuit (IC), the memory controller comprising:

an agent interface unit coupled to receive memory operations input to the memory controller from a plurality of sources within the IC, wherein each received memory operation includes a quality of service (QoS) parameter indicating a requested quality of service for performance of the received memory operation to a memory controlled by the memory controller; and

a plurality of memory channel units, wherein each memory channel unit is configured to control an independent memory channel in a memory coupled to the IC and controlled by the memory controller, wherein the agent interface unit is configured to schedule the received memory operations to the plurality of memory channel units responsive to an address accessed by each received memory operation, and wherein each of the plurality of memory channel units is configured to group memory operations received from the agent interface unit into affinity groups, wherein the memory operations within a given affinity group consume less memory bandwidth when scheduled as a group than when scheduled separately, and wherein each of the plurality of memory channel units is configured to schedule the memory operations to access a memory responsive to a size of the affinity groups and further responsive to the QoS parameters of the memory operations, and wherein each of the plurality of memory channel units is configured to group memory operations into affinity groups and to schedule the memory operations independent of other ones of the plurality of memory channel units.

10. The memory controller as recited in claim 9 wherein each of the plurality of memory channel units is configured to prioritize larger affinity groups over smaller affinity groups for scheduling.

11. The memory controller as recited in claim 10 wherein each of the plurality of memory channel units is configured to schedule a first affinity group having an oldest memory operation with a selected QoS parameter, wherein the selected QoS parameter is determined responsive to a state of the memory controller.

12. The memory controller as recited in claim 11 wherein each of the plurality of memory channel units are configured to eliminate the QoS parameter for write memory operations, and wherein write affinity groups are scheduled based on size of the affinity groups only.

13. The memory controller as recited in claim 11 wherein each of the plurality of memory channel units are configured to schedule a largest affinity group responsive to no affinity groups of the plurality of affinity groups having the selected QoS parameter.

14. An apparatus for a memory controller in an integrated circuit (IC), the apparatus comprising:

a plurality of transaction queues configured to store memory operations from a plurality of sources within the IC and associated quality of service (QoS) parameters, wherein a given QoS parameter indicates a requested quality of service for performance of a corresponding memory operation in a memory to which the integrated circuit is coupled;

an enqueue control unit coupled to the plurality of transaction queues and configured to enqueue memory operations into the plurality of transaction queues, wherein the enqueue control unit is configured to group the memory operations into affinity queues in the plurality of transaction queues, wherein the memory operations within a given affinity group consume less memory bandwidth when scheduled as a group than when scheduled separately; and

a scheduler coupled to the plurality of transaction queues and configured to schedule memory operations for transmission on a memory channel responsive to the affinity queues and further responsive to the QoS parameters, wherein the memory channel is one of a plurality of memory channels in a memory coupled to the memory controller, wherein each channel includes independent affinity queues, transaction queues, and schedulers.

15. The apparatus as recited in claim 14 wherein the affinity queues are virtual queues within the plurality of transaction queues.

16. The apparatus as recited in claim 14 wherein the enqueue control circuit is configured to group memory operations that are page hits, rank misses, or bank misses into an affinity queue.

17. The apparatus as recited in claim 14 wherein the scheduler is configured to favor affinity queues that are more full than other affinity queues in the scheduling.

18. The apparatus as recited in claim 17 wherein the scheduler is configured to favor affinity queues having at least one memory operation that includes a given QoS parameter.

19. The apparatus as recited in claim 18 wherein the given QoS parameter is selected responsive to a state of the memory controller.