Multi-profile memory controller for computing devices

  • US 9,135,190 B1
  • Filed: 09/04/2010
  • Issued: 09/15/2015
  • Est. Priority Date: 09/04/2009
  • Status: Active Grant
First Claim
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1. A method of performing memory transactions on a set of memory locations that includes a first memory location and a second memory location, the method comprising:

  • performing a memory transaction comprising addressing a first memory location in a first memory device in a memory store, said first memory location and a second memory location respectively associated with a first device profile and a second device profile, wherein said second memory location is in a second memory device in the memory store, wherein a memory read transaction or a memory write transaction is performed on at least one of the first memory location or second memory location, wherein data is transferred to the first memory location or second memory location from a host for a memory write transaction, wherein data is transferred from the first memory location or second memory location to the host for a memory read transaction;

    wherein said first device profile is optimal for a data type subject to the memory transaction, wherein said data type comprises one of a random data type or a sequential data type;

    said performing the memory transaction further comprising identifying command details for causing the memory transaction to be performed, wherein said command details comprising the first memory device;

    said first device profile representing a first set of attributes of said first memory location, and said second device profile representing a second set of attributes of said second memory location, and a difference exists between said first and second device profiles;

    after identifying the command details, obtaining the first set of attributes;

    wherein each attribute in the first set of attributes and second set of attributes is associated with a respective attribute qualifier that qualifies a respective memory location;

    wherein the memory store is directly coupled to at least one memory bus and wherein the at least one memory bus is directly coupled to a controller, and wherein the controller performs the memory read transaction and memory write transaction on the memory store;

    wherein the host is directly coupled to the controller by a communication path as the controller performs the memory read transaction or memory write transaction;

    wherein the first device profile and second device profile are each stored in the memory store; and

    using attributes from said first and second device profiles; and

    selecting a transfer size for the memory transaction, wherein the transfer size is a function of a data size of the memory transaction and the first set of attributes.

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