Multiple graphics processing unit display synchronization system and method

• US 9,135,675 B2
• Filed: 06/15/2009
• Issued: 09/15/2015
• Est. Priority Date: 06/15/2009
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Wyatt, David, Modi, Manish
• Primary Examiner(s): Richer, Joni
• Application Number:
  US12/484,954
• Publication Number:
  US 20100315427A1
• Time in Patent Office: 2,283 Days
• Field of Search: 345501-503, 345/505
• US Class Current: 1/1
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06T 3/00 Geometric image transformations in the plane of the image
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 2370/20 Details of the management of multiple sources of image data
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

Systems and methods for utilizing multiple graphics processing units for controlling presentations on a display are presented. In one embodiment, a dual graphics processing system includes a first graphics processing unit for processing graphics information; a second graphics processing unit for processing graphics information; a component for synchronizing transmission of display component information from the first graphics processing unit and the second graphics processing unit and a component for controlling switching between said first graphics processing unit and said second graphics processing unit. In one embodiment, the component for synchronizing transmission of display component information adjusts (e.g., delays, speeds up, etc.) the occurrence or duration of a corresponding graphics presentation characteristic (e.g., end of frame, end of line, vertical blanking period, horizontal blanking period, etc.) in signals from multiple graphics processing units.

Claims

1. A graphics processing system comprising:

a hardware component for transmitting display component information;

a component for adjusting transmission timing of display component information from a first stream of display signals and a second stream of display signals within a synchronization tolerance, wherein said adjusting includes an adjustment to a duration of a timing factor included in a transmission signal of said display component information;

wherein a first pixel source provides said first stream of display signals and a second pixel source provides said second stream of display signals, and wherein said transmission timing adjustment comprises;

a simulation of a generator locking (genlock) function that is performed independently in relation to a genlock hardware component; and

at least one of;

sliding a timing alignment of said first pixel source to match a timing alignment of said second pixel source;

or sliding said timing alignment of said second pixel source to match said timing alignment of said first pixel source; and

a component for switching between said first stream of display signals and said second stream of display signals upon said performance of said transmission timing adjustment; and

wherein upon said switching, an independent timing of said first pixel source and said second pixel source is restored.

2. A graphics processing system of claim 1 further comprising:

a first graphics processing unit for processing graphics information and outputting said first stream of display signals, and

a second graphics processing unit for processing said graphics information and outputting said second stream of display signals.

3. A graphics processing system of claim 2 wherein said component for adjusting transmission of display component information determines a timing difference between a corresponding characteristic of said first stream of display signals and said graphics information.

4. A graphics processing system of claim 3 wherein said timing difference between said corresponding graphics presentation characteristic of said graphics information is a timing difference between corresponding frames of a graphics image.

5. A graphics processing system of claim 3 wherein said timing difference between said corresponding graphics presentation characteristic of said graphics information is a timing difference between corresponding lines of a graphics image.

6. A graphics processing system of claim 2 wherein said component for synchronizing introduces a delay in signals from one of said first graphics processor or said second graphics processor.

7. A graphics processing system of claim 2 wherein said first graphics processing unit is an internal graphics processing unit and said second graphics processing unit is a discrete graphics processing unit.

8. A graphics processing system of claim 1 wherein said component for controlling switching comprises a multiplexer that forwards said first stream of display signals or said second stream of display signals in accordance with a graphics processing unit selection indication.

9. A graphics processing system of claim 1 wherein said component for switching participates in a graphics processing unit change over process comprising changing driving of said first stream of display signals from a first graphics processor to said second stream of display signals from a second graphics processor during a vertical blanking period.

10. A graphics processing method comprising:

performing graphics processing on a first graphics processing unit;

forwarding results of said graphics processing from said first graphics processing unit to a display;

performing graphics processing on a second graphics processing unit;

performing a synchronizing process in which graphics signals from said first graphics processing unit are synchronized to graphics signals from said second graphics processing unit, wherein said synchronizing includes adjusting a time duration between the occurrence of a display characteristic in at least one of said graphics signals;

wherein said synchronizing process comprises simulating a generator locking (genlock) function, which is performed independently in relation to a genlock hardware component, wherein said synchronizing process slides a timing alignment of said first graphics processing unit to match a timing alignment of said second graphics processing unit or vice versa; and

performing a graphics processing unit change over process in which results of said graphics processing from said second graphics processing unit are forwarded to said display instead of said results of said graphics processing from said first graphic processing unit;

wherein upon performance of said graphics processor unit change over process, an independent timing of said first graphics processing unit and an independent timing of said second graphics processing unit are restored.

11. A graphics processing method of claim 10 wherein said first graphics processing unit is an internal graphics processing unit and said second graphics processing unit is a discrete graphics processing unit.

12. A graphics processing method of claim 10 wherein said synchronizing process comprises:

determining a timing difference between a corresponding graphics presentation characteristic of said graphics information processed on said first processor and graphics information processed on said second processor; and

adjusting signals from at least one of said first processor and said second processor to reduce said timing difference between said corresponding graphics presentation characteristic.

13. A graphics processing unit change over process of claim 10 wherein said adjusting signals includes delaying the occurrence or duration of a blanking interval.

14. A graphics processing unit change over process of claim 10 wherein said adjusting signals includes shortening the occurrence of a blanking interval.

15. A programmable non-transitory computer readable storage medium comprising instructions that are tangibly embedded therein for directing a synchronized graphics processing unit change-over process, wherein the graphics processing unit change-over process comprises the steps of:

receiving an indication of timing of a corresponding graphics presentation characteristic of said graphics information processed on a first processor and graphics information processed on a second processor;

determining a difference in said timing of a corresponding graphics presentation characteristic; and

adjusting a duration of at least one of said corresponding graphics presentation characteristics in at least one signal from at least one of said first processor and said second processor to synchronize said occurrence of said corresponding graphics presentation characteristic;

wherein said adjusting a duration comprises simulating a generator locking (genlock) function, which is performed independently in relation to a genlock hardware component, wherein said adjusting slides a timing alignment of said first processor unit to match a timing alignment of said second processor or vice versa; and

wherein upon said synchronization, an independent timing of said first pixel source and said second pixel source is restored.

16. A computer readable medium of claim 15 wherein said corresponding graphics presentation characteristic is a frame blanking interval.

17. A computer readable medium of claim 15 wherein said corresponding graphics presentation characteristic is a line blanking interval.

18. A computer readable medium of claim 15 wherein said adjusting includes adjusting a duration of a blanking interval.

19. A computer readable medium of claim 15 wherein said adjusting includes adjusting an occurrence of a frame blanking interval.

20. A computer readable medium of claim 15 wherein said adjusting includes adjustments to a duration of a vertical blanking period, horizontal blanking period or both.