Switch controls

• US 9,143,124 B2
• Filed: 02/18/2014
• Issued: 09/22/2015
• Est. Priority Date: 02/18/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: ACCO Brands USA LLC (ACCO Brands Incorporated)
• Inventors: Cam, Herv, Venec, Stephanie, Dos Santos, Filipe
• Primary Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US14/183,215
• Publication Number:
  US 20150236691A1
• Time in Patent Office: 581 Days
• Field of Search: 343/786, 455/333, 455/425, 455/550.1
• US Class Current: 1/1
• CPC Class Codes: H01Q 1/50 Structural association of antennas with earthing switches, lead-in devices or lightning protectors
• CPC Class Codes: H01Q 13/02 Waveguide horns
• CPC Class Codes: H03D 7/125 with field effect transistors
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates
• CPC Class Codes: H04B 1/006 using switches for selecting the desired band H04B1/0057 takes precedence
• CPC Class Codes: H04B 1/44 Transmit/receive switching
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence
• CPC Class Codes: H04M 1/724 User interfaces specially adapted for cordless or mobile telephones
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements

Abstract

Switches for use in RF devices are provided that offer a better balance of power losses and switching times than switches of the prior art. Switches of the present invention comprise a stack of transistors controlled a symmetric bias network. The stack of transistors includes an even number of transistors arranged in series, where every two successive transistors defines a pair. The bias network includes a symmetrically branching set of connections, where the gates of every pair of transistors are connected by a first connection having a first node, and two or more first nodes are connected by a second connection to a second node, and so forth. The symmetry of the bias network tends to reject even harmonics, and the rejection of even harmonics can be further enhanced by adding capacitors between the bias network and the stack of transistors at points of symmetry.

Claims

1. A switch comprising:

an even number of transistors arranged in series, each transistor of the number of transistors having a source, a drain, and a gate, every two successive transistors defining a pair of transistors, the number of transistors being at least 4; and

a bias network including

a control line,

for each pair of transistors,

a first connection, including a first node, connecting the gates of the two transistors, the first connection including two first-level resistors, of equal resistance, disposed in series between the gates of the pair of transistors, and

for two pairs of transistors a second connection including a second node connecting the first nodes, the second node being coupled to the control line.

2. The switch of claim 1 wherein the bias network is symmetric,

wherein half of the transistors are on one side of a line of symmetry and the other half of the transistors are on the other side of the line of symmetry, and

wherein the electrical paths through the bias network from a DC control to any two transistors located at a same distance from the line of symmetry are topologically equivalent.

3. The switch of claim 1 wherein each second connection between the second node and each first node comprises a second-level resistor of a same resistance.

4. The switch of claim 1 further comprising a third-level resistor disposed between the control line and a DC control.

5. The switch of claim 1 further comprising, for each transistor, a ladder resistor connected in parallel between the source and the drain of the transistor.

6. The switch of claim 1 wherein, for a central pair of transistors, the first node is connected by a capacitor to a drain of one transistor of the pair and to a source of the other transistor of the pair.

7. The switch of claim 6 wherein, for a first pair of transistors and a second pair of transistors of the number of transistors, the first and second pairs of transistors being equally spaced from and disposed on opposite sides of the central pair, a first capacitor connects a first node of the first pair to a drain of one transistor of the first pair and to a source of the other transistor of first pair, and a second capacitor connects a first node of the second pair to a drain of one transistor of the second pair and to a source of the other transistor of second pair.

8. The switch of claim 1 wherein the switch is defined in CMOS.

9. The switch of claim 1 wherein the switch is defined on a silicon-on-insulator die.

10. An RF device comprising:

a plurality of power amplifiers;

an antenna; and

an antenna switch configured to couple one of the plurality of power amplifiers at a time to the antenna, the antenna switch including, for each power amplifier, a serial switch comprising

an even number of transistors arranged in series, each transistor of the number of transistors having a source, a drain, and a gate, every two successive transistors defining a pair of transistors, the number of transistors being at least 4; and

a bias network including

a control line,

for each pair of transistors,

a first connection, including a first node, connecting the gates of the two transistors, the first connection including two first-level resistors, of equal resistance, disposed in series between the gates of the pair of transistors, and

for two pairs of transistors a second connection including a second node connecting the first nodes, the second node being coupled to the control line.

11. The RF device of claim 10 wherein the bias network is symmetric,

wherein half of the transistors are on one side of a line of symmetry and the other half of the transistors are on the other side of the line of symmetry, and

wherein the electrical paths through the bias network from a DC control to any two transistors located at a same distance from the line of symmetry are topologically equivalent.

12. The RF device of claim 10 wherein each second connection between the second node and each first node comprises a second-level resistor of a same resistance.

13. The RF device of claim 10 further comprising a third-level resistor disposed between the control line and a DC control.

14. The RF device of claim 10 further comprising, for each transistor, a ladder resistor connected in parallel between the source and the drain of the transistor.

15. The RF device of claim 10 wherein, for a central pair of transistors, the first node is connected by a capacitor to a drain of one transistor of the pair and to a source of the other transistor of the pair.

16. The RF device of claim 15 wherein, for a first pair of transistors and a second pair of transistors of the number of transistors, the first and second pairs of transistors being equally spaced from and disposed on opposite sides of the central pair, a first capacitor connects a first node of the first pair to a drain of one transistor of the first pair and to a source of the other transistor of first pair, and a second capacitor connects a first node of the second pair to a drain of one transistor of the second pair and to a source of the other transistor of second pair.

17. The RF device of claim 10 wherein the antenna switch is defined on a silicon-on-insulator die.

18. The RF device of claim 10 wherein the power amplifiers are defined on a first die and the antenna switch is defined on a second die.