Semiconductor package

• US 9,147,643 B2
• Filed: 04/24/2014
• Issued: 09/29/2015
• Est. Priority Date: 04/26/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jinho, You, SE-Ho
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US14/260,415
• Publication Number:
  US 20140319662A1
• Time in Patent Office: 523 Days
• Field of Search: 257/698, 257/700, 257/778, 257/E23.145
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Provided is a semiconductor package which may include a package substrate which includes a power supply region and an interconnection region around the power supply region, a plurality of ground terminals and a plurality of power terminals, which are disposed in the power supply region with a dielectric interposed between the ground terminals and the power terminals, wherein the ground terminals and the power terminals extend from a top surface of the package substrate to a bottom surface of the package substrate, and at least one semiconductor chip mounted on the package substrate, the semiconductor chip includes a plurality of ground pads which are commonly connected to a ground terminal of the ground terminals and a plurality of power pads which are commonly connected to a power terminal of the power terminals.

Claims

1. A semiconductor package, comprising:

a package substrate which comprises a power supply region and an interconnection region around the power supply region;

a ground terminal and a power terminal which are disposed in the power supply region with a dielectric interposed between the ground terminal and the power terminal, wherein the ground terminal and the power terminal extend from a top surface of the package substrate to a bottom surface of the package substrate; and

at least one semiconductor chip mounted on the package substrate comprising a plurality of ground pads which are commonly connected to the ground terminal and a plurality of power pads which are commonly connected to the power terminal.

2. The semiconductor package of claim 1, wherein the power terminal has a closed-loop structure enclosing the ground terminal in plan view.

3. The semiconductor package of claim 1, wherein the power terminal comprises a first power terminal at one side of the ground terminal with the dielectric interposed between the first power terminal and the ground terminal, and a second power terminal at another side of the ground terminal with the dielectric interposed between the second power terminal and the ground terminal.

4. The semiconductor package of claim 1, wherein the package substrate comprises a plurality of insulating layers vertically stacked in the interconnection region and inner interconnection lines disposed between the insulating layers, and

wherein the dielectric is formed of a material having a dielectric constant higher than that of any of the insulating layers.

5. The semiconductor package of claim 4, wherein the ground terminal and the power terminal are electrically separated from the inner interconnection lines.

6. The semiconductor package of claim 1, wherein the ground terminal comprises a plurality of vertically-stacked first conductive patterns and a plurality of first via plugs which electrically connect the vertically-stacked first conductive patterns,

wherein the power terminal comprises a plurality of vertically-stacked second conductive patterns and a plurality of second via plugs which electrically connect the vertically-stacked second conductive patterns.

7. The semiconductor package of claim 1, wherein an area of the ground terminal is larger than that of the power terminal in a plan view.

8. The semiconductor package of claim 1, wherein a number of the ground pads is greater than a number of the power pads.

9. The semiconductor package of claim 1, wherein a plurality of the semiconductor chips are mounted on the package substrate, and

wherein the ground terminal and the power terminal are shared by the semiconductor chips.

10. The semiconductor package of claim 1, wherein the package substrate comprises a plurality of bonding pads which are disposed on a top surface of the interconnection region,

wherein the bonding pads are connected to I/O pads which are used to input and output electrical signals to the at least one semiconductor chip, and

wherein a width of the ground terminal is greater than a width of the bonding pads.

11. The semiconductor package of claim 1, wherein the plurality of ground pads and the plurality of power pads are simultaneously connected to the ground terminal and the power terminal, respectively.

12. The semiconductor package of claim 1, wherein the dielectric interposed between the ground terminal and the power terminal extends continuously and uninterrupted from the top surface of the package substrate to the bottom surface of the package substrate.

13. The semiconductor package of claim 1, wherein the plurality of ground pads and the plurality of power pads are disposed on a bottom surface of the at least one semiconductor chip.

14. A package substrate, comprising:

a substrate comprising a top surface on which a semiconductor chip is mounted, wherein the substrate further comprises a power supply region and an interconnection region around the power supply region;

a plurality of inner interconnection lines disposed in the interconnection region of the substrate to transmit external signals to the semiconductor chip;

a ground terminal disposed in the power supply region of the substrate, and which extends from the top surface of the substrate to a bottom surface of the substrate; and

a power terminal disposed in the power supply region of the substrate, wherein the power terminal is disposed at one side of the ground terminal with a dielectric interposed between the power terminal and the ground terminal such that the power terminal is electrically coupled with the ground terminal,

wherein the around terminal and the power terminal are configured to commonly contact a plurality of ground pads and a plurality of power pads, respectively,of semiconductor chip mounted on the package substrate.

15. The package substrate of claim 14, wherein the substrate comprises a plurality of insulating layers that of the power terminal in a the dielectric.

16. The package substrate of claim 14, wherein the power terminal has a closed-loop structure enclosing the ground terminal in a plan view.

17. The package substrate of claim 14, wherein the power terminal comprises a first power terminal at one side of the ground terminal with the dielectric interposed between the first power terminal and the ground terminal, and a second power terminal at another side of the ground terminal with the dielectric interposed between the second power terminal and the ground terminal.

18. The package substrate of claim 14, wherein the substrate comprises a plurality of bonding pads which are disposed on the top surface of the interconnection region, and

wherein the ground terminal and the power terminal have widths which are greater than the bonding pads.