Embedded capacitive stack

• US 9,161,447 B2
• Filed: 03/10/2008
• Issued: 10/13/2015
• Est. Priority Date: 03/10/2007
• Status: Active Grant

• Current Assignee: Sanmina-SCI Corporation
• Original Assignee: Sanmina-SCI Corporation
• Inventors: Dudnikov, George
• Primary Examiner(s): Patel, Ishwarbhai B
• Application Number:
  US12/045,660
• Publication Number:
  US 20080217049A1
• Time in Patent Office: 2,773 Days
• US Class Current: 1/1
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/306 made by thin film techniques
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/18 Printed circuits structurally associated with non-printed electric components H05K1/0201, H05K1/023, H05K1/0243, and H05K1/16 take precedence
• CPC Class Codes: H05K 2201/0191 wherein the thickness of the dielectric plays an important role
• CPC Class Codes: H05K 2201/0209 Inorganic, non-metallic particles
• CPC Class Codes: H05K 2201/0257 Nanoparticles inks comprising nanoparticles H05K1/097
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2201/093 Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein reduction of cross-talk, noise or interference by patterned shielding planes, ground planes or power planes H05K1/0224
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09518 Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
• CPC Class Codes: H05K 2201/09663 Divided layout, i.e. conductors divided in two or more parts branched layout H05K2201/09254
• CPC Class Codes: H05K 2203/162 Testing a finished product, e.g. heat cycle testing of solder joints patterns for electrical inspection or testing H05K1/0268
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4641 having integrally laminated metal sheets or special power cores
• CPC Class Codes: Y10T 29/43 Electric condenser making
• CPC Class Codes: Y10T 29/435 : Solid dielectric type
• CPC Class Codes: Y10T 29/49036 : including measuring or testing
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

Claims

1. A capacitive stack with high capacitive density, comprising:

a substantially rigid planar core capacitive substrate including a first core dielectric layer sandwiched between a first conductive layer and a second conductive layer,

wherein the planar core capacitive substrate is more rigid than one or more additional conductive and cured dielectric layers stacked and formed onto the planar core capacitive substrate and provides structural rigidity to the additional conductive and dielectric layers,

wherein the first and second conductive layers are each approximately between 0.5-6 mils thick,

wherein the one or more additional conductive and cured dielectric layers include;

a plurality of conductive vias that are electrically coupled to one or more other conductive layers and/or pass through a clearance in the one or more other conductive and cured dielectric layers, and

a plurality of test holes in the additional conductive and cured dielectric layers, wherein the test holes were used to access an exposed underlying conductive layer through an uppermost portion of the test hole, wherein the test holes are distinct from the plurality of conductive vias,

wherein the one or more additional conductive and cured dielectric layers include a cured second dielectric layer coupled to the planar core capacitive substrate, the cured second dielectric layer having a first planar surface coupled to the first conductive layer of the substantially rigid planar core capacitive substrate and being thinner than the first core dielectric layer and including a dielectric material loaded with a nanopowder selected to achieve a desired dielectric constant; and

a first conductive foil coupled to a second planar surface of the second dielectric layer, the first conductive foil is approximately between 0.25-1.5 mils thick.

2. The capacitive stack of claim 1, wherein the second dielectric layer is coated to a thickness of approximately between 0.004 and 1.25 mil.

3. The capacitive stack of claim 1, wherein the second dielectric layer is coated to a thickness of approximately 0.3 mil or less.

4. The capacitive stack of claim 1, wherein the first conductive foil is an ultra-thin foil having a thickness of between 0.12 and 1 mil.

5. The capacitive stack of claim 1, wherein the second dielectric layer provides a capacitive density of between five (5) and sixty (60) nano-Farads per square inch.

6. The capacitive stack of claim 1, wherein the first core dielectric layer is approximately between 0.5-4 mils thick and the second dielectric layer is approximately between 0.3 and 1 mil thick.

7. The capacitive stack of claim 1, further comprising a third dielectric layer having a third planar surface coupled to the second conductive layer, the third dielectric layer being thinner than the first core dielectric layer.

8. The capacitive stack of claim 7, wherein the first conductive layer and a second conductive foil, coupled to a fourth planar surface of the third dielectric layer, serve as power layers while the second conductive layer and first conductive foil serve as ground layers.

9. The capacitive stack of claim 1, wherein the thickness of the third dielectric layer is less than the thickness of the first core dielectric layer.

10. The capacitive stack of claim 1, wherein the second dielectric layer is between 0.004 mils and 0.05 mils.

11. The capacitive stack of claim 1, wherein the second dielectric layer is about 0.004 mils.

12. The capacitive stack of claim 1, further comprising an adhesive layer between the substantially rigid core capacitive substrate and the second dielectric layer.

13. The capacitive stack of claim 1, wherein the conductive layers are each between an eighth of an ounce per square foot foil and a six ounce per square foot foil.

14. The capacitive stack of claim 1, further comprising a third dielectric layer having a third planar surface coupled to the second conductive layer, the third dielectric layer being thinner than the first core dielectric layer, and wherein the first conductive layer and a second conductive foil, coupled to a fourth planar surface of the third dielectric layer, serve as power layers while the second conductive layer and first conductive foil serve as ground layers, and wherein the second dielectric layer is coated to a thickness of approximately between 0.004 and 1.25 mil, the first conductive foil is an ultra-thin foil having a thickness of between 0.12 and 1 mil, the second dielectric layer provides a capacitive density of between five (5) and sixty (60) nano-Farads per square inch, and the first core dielectric layer is approximately between 0.5-4 mils thick.

15. A capacitive stack with high capacitive density, comprising:

a substantially rigid planar core capacitive substrate including a first core dielectric layer sandwiched between a first conductive layer and a second conductive layer,

wherein the planar core capacitive substrate is more rigid than one or more additional conductive and cured dielectric layers stacked and formed onto the planar core capacitive substrate and provides structural rigidity to the additional conductive and dielectric layers,

wherein the one or more additional conductive and cured dielectric layers include a cured second dielectric layer coupled to the planar core capacitive substrate, the cured second dielectric layer having a first planar surface coupled to the first conductive layer of the substantially rigid planar core capacitive substrate, the cured second dielectric layer being thinner than the first core dielectric layer and including a dielectric material loaded with a nanopowder selected to achieve a desired dielectric constant;

a first conductive foil coupled to a second planar surface of the second dielectric layer; and

a pattern of one or more clearances extending from a top surface to a bottom surface of at least one of the first and second conductive layers;

wherein edges of the first and second conductive layers and edges of the one or more additional conductive layers including the first conductive foil are offset from or protrude through one or more edges of the capacitive stack to provide test probe access to the first and second conductive layers and the one or more additional conductive layers,

wherein the first core dielectric layer is approximately between 0.5-4 mils thick, the first and second conductive layers are each approximately between 0.5-6 mils thick, one of the one or more additional cured dielectric layers is approximately between 0.3 and 1 mil thick, and one of the additional conductive layers is approximately between 0.25-1.5 mils thick.

16. The capacitive stack of claim 15, further comprising a third dielectric layer having a third planar surface coupled to the second conductive layer, the third dielectric layer being thinner than the first core dielectric layer.