Column adc

• US 9,164,070 B2
• Filed: 06/30/2011
• Issued: 10/20/2015
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith
• Primary Examiner(s): PATEL, PARESH H
• Application Number:
  US13/174,542
• Publication Number:
  US 20120001616A1
• Time in Patent Office: 1,573 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a column of chemically-sensitive pixels. Each chemically-sensitive pixel may comprise a chemically-sensitive transistor, and a row selection device. The chemical detection circuit may further comprise a column interface circuit coupled to the column of chemically-sensitive pixels and an analog-to-digital converter (ADC) coupled to the column interface circuit. Each column interface circuit and column-level ADC may be arrayed with other identical circuits and share critical resources such as biasing and voltage references, thereby saving area and power.

Claims

1. A chemical detection circuit, comprising:

a column of chemically-sensitive pixels, each pixel comprising;

a chemically-sensitive transistor; and

a row selection device;

a column interface circuit coupled to the column of chemically-sensitive pixels;

an analog-to-digital converter (ADC) coupled to the column interface circuit, the ADC including an offset cancellation circuit;

an output terminal comprising two pins for low-voltage differential signaling; and

a serializer circuit including

a plurality of shift registers to shift data to bit alignment logic for data alignment,

a pair of ping-pong registers to receive the aligned data and latch each parallel word with timing overlap, and

a first multiplexer to select at least one of the ping-pong registers to output data to an encoder;

a serializer coupled to the output terminal and configured to receive encoded data from the encoder; and

a driver to output data from the serializer to the output terminal, wherein the serializer is configured to transmit data signals by low-voltage differential signaling.

2. The chemical detection circuit of claim 1, wherein the chemically-sensitive transistor is an ion-sensitive field effect transistor (ISFET).

3. The chemical detection circuit of claim 2, wherein the row selection device is a non-chemically-sensitive transistor.

4. The chemical detection circuit of claim 3, wherein the ISFET is selected from a group consisting of a N-Metal-Oxide-Semiconductor (NMOS) and a P-Metal-Oxide-Semiconductor (PMOS).

5. The chemical detection circuit of claim 4, wherein the row selection device is selected from the group consisting of an NMOS and a PMOS.

6. The chemical detection circuit of claim 2, wherein the ISFET has a floating gate.

7. The chemical detection circuit of claim 1, wherein the ADC is shared by multiple columns by multiplexing.

8. A chemical sensor, comprising:

a plurality of columns of chemically-sensitive pixels, each column comprising;

a plurality of chemically-sensitive pixels formed in rows, each chemically-sensitive pixel comprising;

a chemically-sensitive transistor; and

a row selection device;

a column interface circuit coupled to the column of chemically-sensitive pixels;

an analog-to-digital converter (ADC) circuit coupled to the column interface circuit, the ADC circuit including an offset cancellation circuit;

an output terminal comprising two pins for low-voltage differential signaling; and

a serializer circuit including

a plurality of shift registers to shift data to bit alignment logic for data alignment,

a pair of ping-pong registers to receive the aligned data and latch each parallel word with timing overlap, and

a first multiplexer to select at least one of the ping-pong registers to output data to an encoder;

a serializer coupled to the output terminal and configured to receive encoded data from the encoder; and

a driver to output data from the serializer to the output terminal, wherein the serializer is configured to transmit data signals by low-voltage differential signaling.

9. The chemical sensor of claim 8, wherein the chemically-sensitive transistor is an ion-sensitive field effect transistor (ISFET).

10. The chemical sensor of claim 9, wherein the row selection device is a non-chemically-sensitive transistor.

11. The chemical sensor of claim 10, wherein the ISFET is selected from a group consisting of a N-Metal-Oxide-Semiconductor (NMOS) and a P-Metal-Oxide-Semiconductor (PMOS).

12. The chemical sensor of claim 11, wherein the row selection device is selected from the group consisting of a NMOS and a PMOS.

13. The chemical sensor of claim 9, wherein the ISFET has a floating gate.

14. The chemical sensor of claim 8, wherein the ADC circuit comprises a plurality of ADCs that each is shared by multiple columns of chemically-sensitive pixels by multiplexing, and the ADCs share bias reference voltages and signal reference voltages for area and power savings.

15. The chemical sensor of claim 8, wherein the ADC circuit comprises a plurality of ADCs that each column of chemically-sensitive pixels has a corresponding ADC, and the ADCs share bias reference voltages and signal reference voltages for area and power savings.