Circuit configured to adjust the activation state of transistors based on load conditions

• US 9,166,028 B2
• Filed: 05/31/2011
• Issued: 10/20/2015
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Feldtkeller, Martin, Deboy, Gerald
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Torres-Rivera, Alex
• Application Number:
  US13/118,993
• Publication Number:
  US 20120306464A1
• Time in Patent Office: 1,603 Days
• Field of Search: 323/217, 323/266, 323/268, 323/282, 257/330, 257/332, 257/334, 257/E29.256, 327/434
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

Disclosed is a circuit arrangement, including a transistor component with a gate terminal, a control terminal, and a load path between a source and a drain terminal, and a drive circuit connected to the control terminal and configured to determine a load condition of the transistor component, to provide a drive potential to the control terminal, and to adjust the drive potential dependent on the load condition.

Claims

1. A circuit arrangement, comprising:

a transistor arrangement comprising a plurality of n transistors, each comprising a gate terminal, and a load path between a source and a drain terminal, and m of the n transistors comprising;

a drift region in the load path between a body region and the drain terminal; and

a control terminal; and

a field electrode arranged in a trench adjacent to and dielectrically insulated from the drift region;

or

a drift control region arranged within a semiconductor body adjacent to and dielectrically insulated from the drift region, and

wherein the gate terminal of the m transistors is coupled to a gate electrode that is dielectrically insulated from the body region and is configured to control an on/off state of the m transistors by controlling a conducting channel in the body region between the source region and the drift region, and wherein the load paths of the plurality of n transistors are connected in parallel forming a load path of the transistor arrangement, where n is an integer number≧

2 and m is an integer number≦

n and m≧

1;

wherein the control terminal of each m transistors is coupled to either the field electrode or the drift control region and is configured to receive a control signal that adjusts an activation state of the m transistors independent from the on/off state, and

a drive circuit configured to independently adjust the activation state of the m transistors to one of a first activation state and a second activation state, to determine a load condition of the transistor arrangement, and to select k transistors that are driven to assume the first activation state and m−

k of the m transistors that are driven to assume the second activation state dependent on the load condition, where k is an integer number≦

m an k≧

0.

2. The circuit arrangement of claim 1, wherein each of the n transistors has an active area of identical size, and k is dependent on the load condition.

3. The circuit arrangement of claim 1, wherein each of the n transistors has an active area of different size, and the drive circuit is configured to select the k transistors that are in the first activation state such that a sum of the sizes of the active areas of the k transistors in the first activation state is dependent on the load condition.

4. The circuit arrangement of claim 1, wherein each of the m transistors has an output capacitance value and is configured to have a voltage dependency of this output capacitance value varied by the control signal.

5. The circuit arrangement of claim 4, wherein each of the m transistors has an on-resistance and is configured to have the on-resistance varied by the corresponding control signal.

6. The circuit arrangement of claim 5, wherein the control signal of each of the m transistors is selected such that the on-resistance is lower in the first activation state than in the second activation state.

7. The circuit arrangement of claim 6, wherein the load condition is dependent on a current flowing through the load path of the transistor arrangement, and the drive circuit is configured to determine a current flowing through the load path of the transistor arrangement, and to select the k transistors driven in the first activation state dependent on the determined current.

8. The circuit arrangement of claim 2, wherein the load condition is dependent on a current flowing through the load path of the transistor arrangement, and k increases with increasing current.

9. The circuit arrangement of claim 3, wherein the load condition is dependent on a current flowing through the load path of the transistor arrangement, and the sum of the sizes of the active areas of the k transistors in the first activation state increases with increasing current.

10. The circuit arrangement of claim 5, wherein the drive circuit is configured to determine a mean value or rms value of the current flowing through the load path of the transistor arrangement within a given time period, and to select the k transistors driven in the first activation state dependent on the determined mean or rms value.

11. The circuit arrangement of claim 1, wherein the drive circuit is further configured to provide at least one gate signal configured to switch the plurality of n transistors on or off.

12. The circuit arrangement of claim 11, wherein the drive circuit is configured to drive the plurality of n transistors to be switched on or to be switched off in common.

13. The circuit arrangement of claim 11, wherein the drive circuit is configured to permanently switch n−

k transistors off.

14. The circuit arrangement of claim 1, the drive circuit is configured to cyclically switch on and off at least some of the plurality of m transistors, the load condition is dependent on a switching frequency of cyclically switching on and off the m transistors, and the drive circuit is configured to set the k transistors driven to assume the first activation state dependent on the switching frequency.

15. The circuit arrangement of claim 2, wherein the load condition is dependent on switching frequency at which the transistor arrangement is cyclically switched on and off, and k decreases with increasing switching frequency.

16. The circuit arrangement of claim 3, wherein the load condition is dependent on switching frequency at which the transistor arrangement is cyclically switched on and off, and the sum of the sizes of the active areas of the k transistors in the first activation state decreases with increasing switching frequency.

17. The circuit arrangement of claim 1, wherein the plurality of n transistors is implemented in one semiconductor body.

18. The circuit arrangement of claim 1, wherein the plurality of n transistors is implemented in at least two semiconductor bodies, and each of the m transistors is implemented in only one of the at least two semiconductor bodies.

19. The circuit arrangement of claim 1, wherein each of the n transistors has a control terminal and the drive circuit provides n drive signals.

20. The circuit arrangement of claim 1, wherein m of the n transistors comprise the drift control region, and wherein the drift control region extends along a complete length of the drift region in a vertical direction of the semiconductor body.

21. The circuit arrangement of claim 20, wherein the drift control region comprises a monocrystalline semiconductor material.

22. A circuit arrangement, comprising:

a transistor arrangement comprising a plurality of n transistors, each comprising a gate terminal, and a load path between a source and a drain terminal, and m of the n transistors comprising;

a drift region in the load path between a body region and the drain terminal; and

a control terminal; and

a field electrode arranged in a trench adjacent to and dielectrically insulated from the drift region;

or

a drift control region arranged within a semiconductor body adjacent to and dielectrically insulated from the drift region; and

wherein the gate terminal of the m transistors is coupled to a gate electrode that is dielectrically insulated from the body region and is configured to control an on/off state of the m transistors, and wherein the load paths of the plurality of n transistors are connected in parallel forming a load path of the transistor arrangement, where n is an integer number≧

2 and m is an integer number≦

n and m≧

1, wherein the control terminal of each m transistors is coupled to either the field electrode or the drift control region and is configured to receive a control signal that adjusts an activation state of the m transistors independent from the on/off state of the m transistors,

a drive circuit configured to independently adjust the activation state of the m transistors to one of a first activation state and a second activation state, to determine a load condition of the transistor arrangement, and to select k transistors that are driven to assume the first activation state and mk of the m transistors that are driven to assume the second activation state dependent on the load condition, where k is an integer number≦

m and k≧

0.