Semiconductor device and method of manufacturing the same

• US 9,166,041 B2
• Filed: 08/14/2014
• Issued: 10/20/2015
• Est. Priority Date: 09/05/2013
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shinohara, Hirofumi, Oda, Hidekazu, Iwamatsu, Toshiaki
• Primary Examiner(s): KIELIN, ERIK J
• Application Number:
  US14/459,999
• Publication Number:
  US 20150061006A1
• Time in Patent Office: 432 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a first active region and a second active region formed of a semiconductor layer formed on the semiconductor substrate via an insulating layer, the first active region and the second active region each being surrounded when seen in a plan view by a device isolation region penetrating through the semiconductor layer and the insulating layer;

a first MISFET formed in the first active region;

a second MISFET formed in the second active region;

a first region and a second region each surrounded when seen in a plan view by the device isolation region and having the semiconductor layer and the insulating layer removed therefrom;

a first semiconductor region of a first conductivity type formed in the semiconductor substrate so as to include the first active region and the first region when seen in a plan view;

a second semiconductor region of the first conductivity type formed in the semiconductor substrate so as to include the first active region and the first region when seen in a plan view and having impurity concentration higher than that of the first semiconductor region;

a third semiconductor region of a second conductivity type that is different from the first conductivity type formed in the semiconductor substrate so as to include the second active region and the second region when seen in a plan view; and

a fourth semiconductor region of the second conductivity type formed in the semiconductor substrate so as to include the second active region and the second region when seen in a plan view and having impurity concentration higher than that of the third semiconductor region,

wherein the second semiconductor region is contained in the first semiconductor region,

the second semiconductor region has a bottom surface at a shallower level than a bottom surface of the first semiconductor region and at a deeper level than a bottom surface of a portion of the device isolation region interposed between the first active region and the first region when seen in a plan view,

the second semiconductor region extends to also under the portion of the device isolation region interposed between the first active region and the first region when seen in a plan view,

the fourth semiconductor region is contained in the third semiconductor region,

the fourth semiconductor region has a bottom surface at a shallower level than a bottom surface of the third semiconductor region and at a deeper level than a bottom surface of a portion of the device isolation region interposed between the second active region and the second region when seen in a plan view, and

the fourth semiconductor region extends to also under the portion of the device isolation region interposed between the second active region and the second region when seen in a plan view.

2. The semiconductor device according to claim 1,

wherein the first semiconductor region and the third semiconductor region are adjacent to each other under the device isolation region,

the second semiconductor region is not in contact with any of the third semiconductor region and the fourth semiconductor region, and

the fourth semiconductor region is not in contact with any of the first semiconductor region and the second semiconductor region.

3. The semiconductor device according to claim 2, further comprising:

a fifth semiconductor region of the first conductivity type formed in the semiconductor substrate so as to face the first active region via the insulating layer and formed so as to be at a shallower level than the bottom surface of the device isolation region and the bottom surface of the second semiconductor region; and

a sixth semiconductor region of the second conductivity type formed in the semiconductor substrate so as to face the second active region via the insulating layer and formed so as to be at a shallower level than the bottom surface of the device isolation region and the bottom surface of the fourth semiconductor region,

wherein the fifth semiconductor region has impurity concentration higher than that of the second semiconductor region,

the fifth semiconductor region has a bottom surface being adjacent to the second semiconductor region,

the sixth semiconductor region has impurity concentration higher than that of the fourth semiconductor region, and

the sixth semiconductor region has a bottom surface being adjacent to the fourth semiconductor region.

4. The semiconductor device according to claim 3,

wherein the first MISFET has a first gate electrode fouled on the first active region via a first gate insulating film, and

the second MISFET has a second gate electrode formed on the second active region via a second gate insulating film.

5. The semiconductor device according to claim 4,

wherein a first plug that is conductive is disposed on the semiconductor substrate in the first region, and

a second plug that is conductive is disposed on the semiconductor substrate in the second region.

6. The semiconductor device according to claim 5,

wherein a voltage for controlling a threshold voltage of the first MISFET is supplied from the first plug via the second semiconductor region to the fifth semiconductor region, and

a voltage for controlling a threshold voltage of the second MISFET is supplied from the second plug via the fourth semiconductor region to the sixth semiconductor region.

7. The semiconductor device according to claim 1,

wherein the bottom surface of the first semiconductor region is at a deeper level than the bottom surface of the device isolation region, and

the bottom surface of the third semiconductor region is at a deeper level than the bottom surface of the device isolation region.

8. The semiconductor device according to claim 1,

wherein the first MISFET is an n-channel-type MISFET,

the second MISFET is a p-channel-type MISFET,

the first conductivity type is p-type, and

the second conductivity type is n-type.

9. The semiconductor device according to claim 1,

wherein the second semiconductor region and the fourth semiconductor region are separated from each other by a portion of the device isolation region interposed between the second semiconductor region and the fourth semiconductor region, and

the portion of the device isolation region interposed between the second semiconductor region and the fourth semiconductor region has a bottom surface at a deeper level than the bottom surface of the second semiconductor region and the bottom surface of the fourth semiconductor region, at a deeper level than the bottom surface of the portion of the device isolation region interposed between the first active region and the first region in the plan view, and at a deeper level than the bottom surface of the portion of the device isolation region interposed between the second active region and the second region in the plan view.

10. A semiconductor device comprising:

a semiconductor substrate;

a first active region and a second active region formed of a semiconductor layer formed on the semiconductor substrate via an insulating layer, the first active region and the second active region each being surrounded when seen in a plan view by a device isolation region penetrating through the semiconductor layer and the insulating layer;

a first MISFET formed in the first active region;

a second MISFET formed in the second active region;

a first region and a second region each surrounded when seen in a plan view by the device isolation region and having the semiconductor layer and the insulating layer removed therefrom;

a first semiconductor region of a first conductivity type formed in the semiconductor substrate so as to include the first active region and the first region when seen in a plan view;

a second semiconductor region of the first conductivity type formed in the semiconductor substrate so as to include the first active region and the first region when seen in a plan view and having impurity concentration higher than that of the first semiconductor region;

a third semiconductor region of a second conductivity type that is different from the first conductivity type formed in the semiconductor substrate so as to include the second active region and the second region when seen in a plan view; and

a fourth semiconductor region of the second conductivity type formed in the semiconductor substrate so as to include the second active region and the second region when seen in a plan view and having impurity concentration higher than that of the third semiconductor region,

wherein the first semiconductor region extends to under the second semiconductor region,

the second semiconductor region has a bottom surface at a shallower level than a bottom surface of the first semiconductor region and at a deeper level than a bottom surface of a portion of the device isolation region interposed between the first active region and the first region when seen in a plan view,

the second semiconductor region extends to also under the portion of the device isolation region interposed between the first active region and the first region when seen in a plan view,

the third semiconductor region extends to under the fourth semiconductor region,

the fourth semiconductor region has a bottom surface at a shallower level than a bottom surface of the third semiconductor region and at a deeper level than a bottom surface of a portion of the device isolation region interposed between the second active region and the second region when seen in a plan view,

the fourth semiconductor region extends to also under the portion of the device isolation region interposed between the second active region and the second region when seen in a plan view,

the second semiconductor region and the fourth semiconductor region are separated from each other by a portion of the device isolation region interposed between the second semiconductor region and the fourth semiconductor region, and

the portion of the device isolation region interposed between the second semiconductor region and the fourth semiconductor region has a bottom surface at a deeper level than the bottom surface of the second semiconductor region and the bottom surface of the fourth semiconductor region, at a deeper level than the bottom surface of the portion of the device isolation region interposed between the first active region and the first region when seen in a plan view, and at a deeper level than the bottom surface of the portion of the device isolation region interposed between the second active region and the second region when seen in a plan view.

11. The semiconductor device according to claim 10,

wherein the first semiconductor region and the third semiconductor region are adjacent to each other under the device isolation region,

the second semiconductor region is not in contact with any of the third semiconductor region and the fourth semiconductor region, and

the fourth semiconductor region is not in contact with any of the first semiconductor region and the second semiconductor region.

12. A semiconductor device manufacturing method comprising the steps of:

(a) preparing a substrate, the substrate including a semiconductor substrate that has a first region, a second region, a third region, and a fourth region on a main surface of the semiconductor substrate, an insulating layer formed on the main surface of the semiconductor substrate, and a semiconductor layer formed on the insulating layer;

(b) forming, on the substrate, a device isolation region penetrating through the semiconductor layer and the insulating layer so that the first region, the second region, the third region, and the fourth region are each surrounded by the device isolation region when seen in a plan view;

(c) after the step (b), forming a first semiconductor region of a first conductivity type in the semiconductor substrate so as to include the first region and the third region when seen in a plan view;

(d) after the step (b), forming a second semiconductor region of the first conductivity type in the semiconductor substrate so as to include the first region and the third region when seen in a plan view;

(e) after the step (b), forming a third semiconductor region of a second conductivity type that is opposite to the first conductivity type in the semiconductor substrate so as to include the second region and the fourth region when seen in a plan view;

(f) after the step (b), forming a fourth semiconductor region of the second conductivity type in the semiconductor substrate so as to include the second region and the fourth region when seen in a plan view;

(g) after the step (b), removing the semiconductor layer and the insulating layer on the semiconductor substrate in the first region and the second region; and

(h) after the steps (b), (c), (d), (e), (f), and (g), forming a first MISFET in the semiconductor layer that is remaining via the insulating layer on the semiconductor substrate in the third region and forming a second MISFET in the semiconductor layer that is remaining via the insulating layer on the semiconductor substrate in the fourth region,

wherein the second semiconductor region has impurity concentration higher than that of the first semiconductor region, is contained in the first semiconductor region, and is shallower than the first semiconductor region,

the fourth semiconductor region has impurity concentration higher than impurity concentration of the third semiconductor region, is contained in the third semiconductor region, and is shallower than the third semiconductor region,

the second semiconductor region has a bottom surface at a deeper level than a bottom surface of a portion of the device isolation region interposed between the first region and the third region when seen in a plan view,

the second semiconductor region extends to also under a portion of the device isolation region interposed between the first region and the third region when seen in a plan view,

the fourth semiconductor region has a bottom surface at a deeper level than a bottom surface of a portion of the device isolation region interposed between the second region and the fourth region when seen in a plan view, and

the fourth semiconductor region extends to also under a portion of the device isolation region interposed between the second region and the fourth region when seen in a plan view.

13. The semiconductor device manufacturing method according to claim 12,

wherein the first semiconductor region and the third semiconductor region are adjacent to each other under the device isolation region.

14. The semiconductor device manufacturing method according to claim 13, further comprising:

(i) after the step (b) and before the step (g), forming a fifth semiconductor region of the first conductivity type in the semiconductor substrate in the third region; and

(j) after the step (b) and before the step (g), forming a sixth semiconductor region of the second conductivity type in the semiconductor substrate in the fourth region,

wherein the fifth semiconductor region has impurity concentration higher than that of the second semiconductor region, and is formed at a shallower level than the bottom surface of the device isolation region and the bottom surface of the second semiconductor region, and

the sixth semiconductor region has impurity concentration higher than that of the fourth semiconductor region, and is formed at a shallower level than the bottom surface of the device isolation region and the bottom surface of the fourth semiconductor region.

15. The semiconductor device manufacturing method according to claim 14,

wherein, in the step (c), the first semiconductor region is formed by ion implantation,

in the step (d), the second semiconductor region is formed by ion implantation,

in the step (e), the third semiconductor region is formed by ion implantation,

in the step (f), the fourth semiconductor region is formed by ion implantation,

in the step (i), the fifth semiconductor region is formed by ion implantation,

in the step (j), the sixth semiconductor region is formed by ion implantation,

in the step (d) and the step (i), a first common mask layer formed on the substrate is used as an ion implantation blocking mask, and

in the step (f) and the step (j), a second common mask layer formed on the substrate is used as an ion implantation blocking mask.

16. The semiconductor device manufacturing method according to claim 14, wherein

in the step (c), the first semiconductor region is formed by ion implantation,

in the step (d), the second semiconductor region is formed by ion implantation,

in the step (e), the third semiconductor region is formed by ion implantation,

in the step (f), the fourth semiconductor region is formed by ion implantation,

in the step (i), the fifth semiconductor region is formed by ion implantation,

in the step (j), the sixth semiconductor region is formed by ion implantation, and,

in the step (c) and the step (e), angled ion implantation is used.

17. The semiconductor device manufacturing method according to claim 16,

wherein in the steps (c), the step (d), and the step (i), a first common mask layer on the substrate is used as an ion implantation blocking mask, and,

in the step (e), the step (f), and the step (j), a second common mask layer on the substrate is used as an ion implantation blocking mask.

18. The semiconductor device manufacturing method according to claim 12,

wherein the first MISFET is an n-channel-type MISFET,

the second MISFET is a p-channel-type MISFET,

the first conductivity type is a p-type, and

the second conductivity type is an n-type.

19. The semiconductor device manufacturing method according to claim 12, wherein the second semiconductor region and the fourth semiconductor region are separated from each other by a portion of the device isolation region interposed between the second semiconductor region and the fourth semiconductor region, and

the portion of the device isolation region interposed between the second semiconductor region and the fourth semiconductor region has a bottom surface at a deeper level than the bottom surface of the second semiconductor region and the bottom surface of the fourth semiconductor region, at a deeper level than the bottom surface of the portion of the device isolation region interposed between the first region and the third region in the plan view, and a deeper level than the bottom surface of the portion of the device isolation region interposed between the second region and the fourth region in the plan view.