N factorial dual data rate clock and data recovery

• US 9,178,690 B2
• Filed: 04/14/2014
• Issued: 11/03/2015
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro
• Primary Examiner(s): Garcia, Santiago
• Application Number:
  US14/252,450
• Publication Number:
  US 20150098536A1
• Time in Patent Office: 568 Days
• Field of Search: 375/355
• US Class Current: 1/1
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828
• CPC Class Codes: H04L 25/4923 using ternary codes H04L25/4927 takes precedence
• CPC Class Codes: H04L 5/0053 Allocation of signaling, i.e. of overhead other than pilot signals
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.

Claims

1. A method of data communications, comprising:

receiving a sequence of symbols from a plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval;

generating a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval;

generating a second clock signal from transitions in signaling state of the plurality of signal wires occurring between each even transmission interval and a consecutive odd transmission interval;

using the first clock signal to capture a first set of symbols comprising symbols in the sequence of symbols that are received in even transmission intervals; and

using the second clock signal to capture a second set of symbols comprising symbols in the sequence of symbols that are received in odd transmission intervals.

2. The method of claim 1, wherein each odd transmission interval is immediately preceded by a first even transmission interval and immediately succeeded by a second even transmission interval.

3. The method of claim 1, wherein each pair of consecutive symbols received in the sequence of symbols comprises one symbol received during in an odd transmission interval and one symbol received during an even transmission interval.

4. The method of claim 1, wherein timing of a first edge in the first clock signal is based on a first transition that occurs between a first symbol and a second symbol that is received immediately after the first symbol, and wherein timing of a first edge in the second clock signal is based on a second transition that occurs between the second symbol and a third symbol that is received immediately after the second symbol.

5. The method of claim 4, wherein timing of a second edge in the first clock signal is based on the timing of the first edge in the second clock signal, and wherein timing of a second edge in the second clock signal is based on timing of a third edge in the first clock signal, the timing of the third edge in the first clock signal being based on a third transition that occurs between the third symbol and a fourth symbol that is received immediately after the third symbol.

6. The method of claim 4, wherein generating the first clock signal comprises:

ignoring the second transition.

7. The method of claim 4, wherein generating the second clock signal comprises:

ignoring the first transition.

8. The method of claim 1, wherein each pair of consecutive symbols in the sequence of symbols includes two symbols that are associated with different signaling states on the plurality of signal wires.

9. The method of claim 1, wherein receiving the sequence of symbols from the plurality of signal wires comprises:

receiving differential signals from all possible combinations of two signal wires in the plurality of signal wires, wherein each symbol in the sequence of symbols is encoded in a combination of signaling states of the differential signals.

10. The method of claim 1, wherein receiving the sequence of symbols from the plurality of signal wires comprises:

receiving a 3-phase signal from each of three signal wires, wherein each of the three signal wires is in a different signaling state with respect to the other signal wires in each transmission interval, and wherein each symbol in the sequence of symbols is encoded in a combination of signaling states of the three signal wires.

31. The method of claim 1, further wherein each symbol in the sequence of symbols defines a signaling state of the plurality of signal wires for a corresponding transmission interval, and data is encoded in a difference in value between symbols in each pair of consecutive symbols in the sequence of symbols.

11. An apparatus, comprising:

means for receiving a sequence of symbols from a plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval;

means for generating a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval;

means for generating a second clock signal from transitions in signaling state of the plurality of signal wires occurring between each even transmission interval and a consecutive odd transmission interval;

means for using the first clock signal to capture a first set of symbols comprising symbols in the sequence of symbols that are received in even transmission intervals; and

means for using the second clock signal to capture a second set of symbols comprising symbols in the sequence of symbols that are received in odd transmission intervals.

12. The apparatus of claim 11, wherein each odd transmission interval is immediately preceded by a first even transmission interval and immediately succeeded by a second even transmission interval.

13. The apparatus of claim 11, wherein each pair of consecutive symbols received in the sequence of symbols comprises one symbol received during in an odd transmission interval and one symbol received during an even transmission interval.

14. The apparatus of claim 11, wherein timing of a first edge in the first clock signal is based on a first transition that occurs between a first symbol and a second symbol that is received immediately after the first symbol, and wherein timing of a first edge in the second clock signal is based on a second transition that occurs between the second symbol and a third symbol that is received immediately after the second symbol.

15. The apparatus of claim 14, wherein timing of a second edge in the first clock signal is based on the timing of the first edge in the second clock signal, and wherein timing of a second edge in the second clock signal is based on timing of a third edge in the first clock signal, the timing of the third edge in the first clock signal being based on a third transition that occurs between the third symbol and a fourth symbol that is received immediately after the third symbol.

16. The apparatus of claim 14, wherein the means for generating the first clock signal is adapted to ignore the second transition.

17. The apparatus of claim 14, wherein the means for generating the second clock signal is adapted to ignore the first transition.

18. The apparatus of claim 11, wherein each pair of consecutive symbols in the sequence of symbols includes two symbols that are associated with different signaling states on the plurality of signal wires.

19. The apparatus of claim 11, wherein the means for receiving the sequence of symbols from the plurality of signal wires is configured to receive differential signals from all possible combinations of two signal wires in the plurality of signal wires, wherein each symbol in the sequence of symbols is encoded in a combination of signaling states of the differential signals.

20. The apparatus of claim 11, wherein the means for receiving the sequence of symbols from the plurality of signal wires is configured to receive a 3-phase signal from each of three signal wires, wherein each of the three signal wires is in a different signaling state with respect to the other signal wires in each transmission interval, and wherein each symbol in the sequence of symbols is encoded in a combination of signaling states of the three signal wires.

21. A receiver, comprising:

a plurality of line interface circuits configured to receive signals from a plurality of signal wires; and

a clock and data recovery circuit configured to;

receive a sequence of symbols from the plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval;

generate a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval;

generate a second clock signal from transitions in signaling state of the plurality of signal wires occurring between each even transmission interval and a consecutive odd transmission interval;

use the first clock signal to capture a first set of symbols comprising symbols in the sequence of symbols that are received in even transmission intervals; and

use the second clock signal to capture a second set of symbols comprising symbols in the sequence of symbols that are received in odd transmission intervals.

22. The receiver of claim 21, wherein timing of a first edge in the first clock signal is based on a first transition that occurs between a first symbol and a second symbol that is received immediately after the first symbol, and wherein timing of a first edge in the second clock signal is based on a second transition that occurs between the second symbol and a third symbol that is received immediately after the second symbol.

23. The receiver of claim 22, wherein timing of a second edge in the first clock signal is based on the timing of the first edge in the second clock signal, and wherein timing of a second edge in the second clock signal is based on timing of a third edge in the first clock signal, the timing of the third edge in the first clock signal being based on a third transition that occurs between the third symbol and a fourth symbol that is received immediately after the third symbol.

24. The receiver of claim 22, wherein the first transition is ignored by circuitry that generates the second clock signal, and wherein the second transition is ignored by circuitry that generates the first clock signal.

25. The receiver of claim 21, wherein each pair of consecutive symbols in the sequence of symbols includes two symbols that are associated with different signaling states on the plurality of signal wires.

26. A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

receive a sequence of symbols from a plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval;

generate a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval;

generate a second clock signal from transitions in signaling state of the plurality of signal wires occurring between each even transmission interval and a consecutive odd transmission interval;

use the first clock signal to capture a first set of symbols comprising symbols in the sequence of symbols that are received in even transmission intervals; and

use the second clock signal to capture a second set of symbols comprising symbols in the sequence of symbols that are received in odd transmission intervals.

27. The non-transitory processor-readable storage medium of claim 26, wherein timing of a first edge in the first clock signal is based on a first transition that occurs between a first symbol and a second symbol that is received immediately after the first symbol, and wherein timing of a first edge in the second clock signal is based on a second transition that occurs between the second symbol and a third symbol that is received immediately after the second symbol.

28. The non-transitory processor-readable storage medium of claim 27, wherein timing of a second edge in the first clock signal is based on the timing of the first edge in the second clock signal, and wherein timing of a second edge in the second clock signal is based on timing of a third edge in the first clock signal, the timing of the third edge in the first clock signal being based on a third transition that occurs between the third symbol and a fourth symbol that is received immediately after the third symbol.

29. The non-transitory processor-readable storage medium of claim 27, wherein the one or more instructions cause the at least one processing circuit to:

ignore the first transition when generating the second clock signal.

30. The non-transitory processor-readable storage medium of claim 27, wherein the one or more instructions cause the at least one processing circuit to:

ignore the second transition when generating the first clock signal.