System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class

• US 9,182,914 B1
• Filed: 01/05/2015
• Issued: 11/10/2015
• Est. Priority Date: 04/06/2011
• Status: Active Grant

• Current Assignee: P4tents1 LLC
• Original Assignee: P4tents1 LLC
• Inventors: Smith, Michael S
• Primary Examiner(s): Cardwell, Eric S
• Application Number:
  US14/589,940
• Time in Patent Office: 309 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0824 Distributed directories, e.g. linked lists of caches
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 9/44557 Code layout in executable memory
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including a first memory of a first memory class, and a second memory of a second memory class communicatively coupled to the first memory. In operation, data is fetched using a time between a plurality of threads.

Claims

1. An apparatus, comprising:

a plurality of memories including NAND flash memory and random access memory;

a first circuit for receiving DDR signals and outputting SATA signals, the first circuit capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and

a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory;

said DDR protocol being operable for allowing a single complete read or write operation in response to a single read or write command;

said apparatus configured for;

receiving, at the first circuit via the first bus, a first command for initiating a particular single complete read or write operation in connection with particular information;

after the receipt of the first command, making the particular information that is in one of the plurality of memories available in another one of the plurality of memories, utilizing the second circuit; and

receiving, at the first circuit via the first bus, a second command for completing the particular single complete read or write operation in connection with the particular information.

2. The apparatus of claim 1, wherein the apparatus is configured such that the DDR protocol is operable for allowing the single complete read or write operation in response to the single read or write command, per a specification of a JEDEC standard.

3. The apparatus of claim 2, wherein the apparatus is configured such that the particular single complete read or write operation requires both the first command and the second command to complete the particular single complete read or write operation in connection with the particular information, in a manner undescribed in the specification of the JEDEC standard.

4. The apparatus of claim 1, wherein the apparatus is configured such that, despite the DDR protocol being operable for allowing the single complete read or write operation in response to the single read or write command, the particular single complete read or write operation requires both the first command and the second command to complete the particular single complete read or write operation in connection with the particular information, to accommodate the particular information that is in the one of the plurality of memories to be made available in the another one of the plurality of memories, utilizing the second circuit.

5. The apparatus of claim 1, wherein the apparatus is configured such that the single complete read or write operation includes a single complete read operation.

6. The apparatus of claim 1, wherein the apparatus is configured such that the single complete read or write operation includes a single complete read operation that includes a plurality of sub-operations for performing the single complete read operation.

7. The apparatus of claim 1, wherein the apparatus is configured such that the single complete read or write operation includes a single complete read operation that includes a plurality of sub-operations involving operating on different portions of the particular information that are in different portions of the one of the plurality of memories.

8. The apparatus of claim 1, wherein the apparatus is configured such that the single read or write command is received by a central processor.

9. The apparatus of claim 1, wherein the apparatus is configured such that the particular single complete read or write operation is initiated by making the particular information that is in the one of the plurality of memories available in the another one of the plurality of memories.

10. The apparatus of claim 1, wherein the apparatus is configured such that the particular information that is in the one of the plurality of memories is made available in the another one of the plurality of memories by writing the particular information to the another one of the plurality of memories.

11. The apparatus of claim 1, wherein the apparatus is configured such that the particular single complete read or write operation is completed by sending the particular information to at least one processor.

12. The apparatus of claim 1, wherein the apparatus is configured such that an execution of at least one of a plurality of threads involves the first command that is required to be received from a processing unit utilizing the DDR protocol for initiating the particular single complete read or write operation.

13. The apparatus of claim 12, wherein the apparatus is configured such that the execution of at least another one of the plurality of threads involves the second command that is required to be received from the processing unit utilizing the DDR protocol for completing the particular single complete read or write operation.

14. The apparatus of claim 1, wherein the apparatus is configured such that, after the receipt of the first command but before the particular information that is in the one of the plurality of memories is made available in the another one of the plurality of memories, the apparatus is configured for receiving and processing an additional command for initiating an additional single complete read or write operation.

15. The apparatus of claim 1, wherein the apparatus is configured such that, after the receipt of the first command but before a status is provided, the apparatus is configured for receiving and processing an additional command for initiating an additional single complete read or write operation.

16. The apparatus of claim 1, wherein the apparatus is configured such that, after the receipt of the first command but before the completion of the particular single complete read or write operation, the apparatus is configured for receiving and processing an additional command for initiating a subsequent particular single complete read or write operation.

17. The apparatus of claim 1, wherein the apparatus is configured such that the first command causes at least a portion of a random access data read.

18. The apparatus of claim 17, wherein the apparatus is configured such that the random access data read is one of a plurality of random access reads interspersed with a plurality of random access writes.

19. The apparatus of claim 17, wherein the apparatus is configured such that the random access data read is one of a plurality of random access reads interleaved with a plurality of random access writes performed in real-time.

20. The apparatus of claim 17, wherein the apparatus is configured such that the random access data read includes an access in connection with at least one of an arbitrary time or an arbitrary address.

21. The apparatus of claim 1, and further comprising an additional memory that is of a class that is different from at least one of the NAND flash memory or the random access memory.

22. The apparatus of claim 21, wherein the apparatus is configured such that the additional memory is of a class that is different from both the NAND flash memory and the random access memory.

23. The apparatus of claim 21, wherein the apparatus is configured such that the additional memory is part of the first circuit.

24. The apparatus of claim 21, and further comprising another additional memory that is of a class that is different from the additional memory.

25. The apparatus of claim 24, wherein the apparatus is configured such that the another additional memory is part of the first circuit.

26. The apparatus of claim 21, and further comprising another additional memory that is of a class that is different from the additional memory, the NAND flash memory, and the random access memory.

27. The apparatus of claim 21, wherein the apparatus is configured such that a random access data read from the NAND flash memory is carried out utilizing the additional memory.

28. The apparatus of claim 1, wherein the apparatus is configured such that at least a portion of the first command is stored in at least one table in memory in the first circuit.

29. The apparatus of claim 1, wherein the apparatus is configured such that the first command includes a special read command for causing a random access data read operation.

30. The apparatus of claim 1, wherein the apparatus is configured such that at least one of the first command or the second command is capable of being addressed to a particular memory location.

31. The apparatus of claim 30, wherein the apparatus is configured such that the particular memory location includes a predetermined particular memory location.

32. The apparatus of claim 30, wherein the apparatus is configured such that the particular memory location includes a special memory location.

33. The apparatus of claim 30, wherein the apparatus is configured such that the particular memory location is incapable of being subject of standard addressing under the DDR protocol.

34. The apparatus of claim 30, wherein the apparatus is configured such that the particular memory location is capable of standard addressing under a specification of a JEDEC standard, but is also capable of being used in a way that is undescribed in the specification of the JEDEC standard.

35. The apparatus of claim 30, wherein the apparatus is configured such that the particular information that is in the one of the plurality of memories is made available in the another one of the plurality of memories, based at least in part on the first command being addressed to the particular memory location.

36. The apparatus of claim 30, wherein the apparatus is configured such that the particular information that is in the one of the plurality of memories is made available in the another one of the plurality of memories, based on the at least one of the first command or the second command being addressed to the particular memory location.

37. The apparatus of claim 30, wherein the apparatus is configured such that the at least one of the first command or the second command is capable of being addressed to the particular memory location for allowing communication of control to the apparatus.

38. The apparatus of claim 1, wherein the apparatus is configured such that the first command is one of a plurality of commands that allow an input of control via the first bus associated with the DDR protocol, the plurality of commands further including at least one additional command that is capable of being addressed to a particular random access memory location, that is capable of standard addressing under a specification of a JEDEC standard but is also capable of being used in a way that is undescribed in the specification of the JEDEC standard, for allowing the input of the control via the first bus associated with the DDR protocol.

39. The apparatus of claim 1, wherein the apparatus is configured such that the one of the plurality of memories includes the NAND flash memory and the another one of the plurality of memories includes the random access memory.

40. The apparatus of claim 1, wherein the apparatus is configured such that the one of the plurality of memories includes the random access memory and the another one of the plurality of memories includes the NAND flash memory.

41. The apparatus of claim 1, wherein the apparatus is configured such that the first circuit causes the particular information that is in the one of the plurality of memories to be made available in the another one of the plurality of memories, by sending a standard command to the second circuit.

42. An apparatus, comprising:

a plurality of memories including NAND flash memory and random access memory;

first circuitry configured to receive DDR signals and output SATA signals, the first circuitry configured for being communicatively coupled to a first bus for use with a DDR protocol; and

second circuitry configured to receive the SATA signals and output NAND flash signals, the second circuitry communicatively coupled to the first circuitry via a second bus, the second circuitry further communicatively coupled to the NAND flash memory;

said apparatus configured for;

receiving, by the first circuitry via the first bus, a first command, for initiating a particular single complete read or write operation on particular information;

after the receipt of the first command, making the particular information that is in one of the plurality of memories available in another one of the plurality of memories;

receiving, by the first circuitry via the first bus, a second command; and

after the receipt of the second command, sending, to at least one processor via the first bus, the particular information, for completing the particular single complete read or write operation on the particular information;

said apparatus configured such that, despite the first bus being operable for allowing a single complete read or write operation after a single read or write command is received by the at least one processor, the particular single complete read or write operation requires both the first command and the second command to complete the particular single complete read or write operation on the particular information, to support the particular information that is in the one of the plurality of memories being made available in the another one of the plurality of memories.

43. An apparatus, comprising:

a plurality of memories including NAND flash memory and random access memory;

first circuitry configured to receive DDR signals via a first bus;

the first circuitry further configured to output SATA signals; and

second circuitry configured to receive the SATA signals via a second bus, the second circuitry further configured to output NAND flash signals via a third bus;

said first bus being operable for communicating one read or write command that corresponds with one read or write operation;

said apparatus configured for;

receiving, by the first circuitry via the first bus, a first command for a particular read or write operation on particular information;

after the receipt of the first command, writing the particular information that is in one of the plurality of memories to another one of the plurality of memories, utilizing the second circuitry; and

receiving, by the first circuitry via the first bus, a second command for the particular read or write operation on the particular information.

44. An apparatus, comprising:

NAND flash memory means;

random access memory means;

first means for receiving DDR signals via a first bus using a DDR protocol; and

second means for receiving SATA signals and outputting NAND flash signals;

said DDR protocol being operable for allowing a single complete read operation in response to a single read command;

said apparatus configured for;

receiving, via the first bus, a first command for initiating a particular single complete read operation on particular information;

after the receipt of the first command, making the particular information available in at least one of the NAND flash memory means or the random access memory means; and

receiving, via the first bus, a second command for completing the particular single complete read operation on the particular information.