Thermoelectric device
First Claim
Patent Images
1. A thermoelectric device, comprising:
- at least one module having a first carrier layer and a second carrier layer, said first carrier layer and said second carrier layer defining an interspace therebetween;
electrical insulation layers disposed on said first carrier layer and on said second carrier layer toward said interspace; and
a plurality of p and n-doped semiconductor elements, disposed alternately in said interspace between said electrical insulation layers and said p and n-doped semiconductor elements are alternately electrically connected to one another, said p and n-doped semiconductor elements are each configured in an annular shape and having an outer circumferential area and an inner circumferential area, said p and n-doped semiconductor elements connected to said electrical insulation layers by said outer circumferential area and said inner circumferential area, said p and n-doped semiconductor elements each having current transfer areas on said outer circumferential area and on said inner circumferential area, said current transfer areas of said outer circumferential area and of said inner circumferential area of a respective one of said p and n-doped semiconductor elements have the same surface area size.
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Abstract
A thermoelectric device contains at least one module having a first carrier layer and a second carrier layer, an interspace disposed between the first carrier layer and the second carrier layer, and an electrical insulation layer disposed on each of the first carrier layer and on the second carrier layer toward the interspace. The thermoelectric device further has a plurality of p and n-doped semiconductor elements, which are arranged alternately in the interspace between the insulation layers and are alternately electrically connected to one another.
19 Citations
12 Claims
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1. A thermoelectric device, comprising:
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at least one module having a first carrier layer and a second carrier layer, said first carrier layer and said second carrier layer defining an interspace therebetween; electrical insulation layers disposed on said first carrier layer and on said second carrier layer toward said interspace; and a plurality of p and n-doped semiconductor elements, disposed alternately in said interspace between said electrical insulation layers and said p and n-doped semiconductor elements are alternately electrically connected to one another, said p and n-doped semiconductor elements are each configured in an annular shape and having an outer circumferential area and an inner circumferential area, said p and n-doped semiconductor elements connected to said electrical insulation layers by said outer circumferential area and said inner circumferential area, said p and n-doped semiconductor elements each having current transfer areas on said outer circumferential area and on said inner circumferential area, said current transfer areas of said outer circumferential area and of said inner circumferential area of a respective one of said p and n-doped semiconductor elements have the same surface area size. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A motor vehicle, comprising:
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an internal combustion engine; an exhaust gas system; a cooling circuit; and a plurality of thermoelectric devices each containing; a hot side connected to said exhaust gas system; a cold side connected to said cooling circuit; at least one module having a first carrier layer and a second carrier layer, said first carrier layer and said second carrier layer defining an interspace therebetween; electrical insulation layers disposed on said first carrier layer and on said second carrier layer toward said interspace; a plurality of p and n-doped semiconductor elements, disposed alternately in said interspace between said electrical insulation layers and said p and n-doped semiconductor elements are alternately electrically connected to one another, each of said p and n-doped semiconductor elements having an annular shape; said first carrier layer connected to the hot side and said second carrier layer connected to the cold side; and each of said p and n-doped semiconductor elements having a first contact area connected to one of said electrical insulation layers and said one of said electrical insulation layers is connected to said first carrier layer and a second contact area connected to another one of said electrical insulation layers and said another one of said electrical insulation layers is connected to said second carrier layer, said first and second contact areas having contact surfaces of different surface area sizes, said p and n-doped semiconductor elements each having current transfer areas on said first contact area and on said second contact area, said current transfer areas of said first and second contact areas of a respective one of said p and n-doped semiconductor elements being of a same surface area size.
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Specification